一种开关电流电路时钟馈通的补偿技术

提出一种开关电流电路时钟馈通的补偿技术.这种技术可以同时取消误差电流中的常数项和信号关联项.在相同工艺条件下的HSPICE仿真结果表明:文中提出的时钟馈通补偿技术的开关电流存储单元与基本的开关电流存储单元相比,误差电流减小了100倍.     

一种开关电流电路时钟馈通的补偿技术

提出一种开关电流电路时钟馈通的补偿技术.这种技术可以同时取消误差电流中的常数项和信号关联项.在相同工艺条件下的HSPICE仿真结果表明:文中提出的时钟馈通补偿技术的开关电流存储单元与基本的开关电流存储单元相比,误差电流减小了10 0倍.     

开关电流电路及其误差分析

开关电流(SI)技术是有望取代开关电容技术的一种新的采样数据技术。首先介绍了开关电流技术的概念及优点,然后以SI电路基本存储单元为例分析了开关电流电路中可能存在的误差。最后,针对电路中存在的失配误差、传输误差、噪声误差及电荷注入误差等提出了一些解决方法,如S2I技术等。     

实时时钟电路的原理及应用

介绍美国DALLAS公司推出的具有涓细电流充电能力的低功耗实时时钟电路DS1302的结构、工作原理及其在实时显示时间中的应用。它可以对年、月、日、周日、时、分、秒进行计时，且具有闰年补偿等多种功能。给出DS1302在读写中的C51程序及流程图，以及在调试过程中的注意事项。     

DSP系统中时钟电路的设计

在 DSP 系统中,时钟电路是处理数字信息的基础,　同时它也是产生电磁辐射的主要来源,其性能好坏直接影响到系统是否正常运行,所以时钟电路在数字系统设计中占有至关重要的地位。下面主要以TI公司的产品为例介绍DSP系统中时钟电路的设计。1.时钟电路的种类TI　DSP系统中的时钟电     

时钟电路的电磁波干扰

所有会产生电压频率信号的电子组件都是潜在的电磁波干扰(EMI)的来源，这些电磁波信号将会影响如收音机、电视或移动电话等电子产品的正常运作。大多数系统中产生电磁波噪声的主要来源是系统时钟的产生与分配电路，本文将探讨电磁波干扰产生的原因、如何测量电磁波干扰及如何降低电磁波干扰带来的影响。     

时钟电路的电磁兼容设计

时钟电路是数字电路的重要组成部分,其电磁兼容设计是一个复杂的问题。文章在分柝脉冲频谱特性的基础上,研究了时钟电路的电磁干扰问题,提出了时钟电路电磁兼容设计的基本方法。     

霍尔传感器在时钟电路中的应用

利用霍尔传感器,我设计出了一款时钟电路,而这款时钟电路不单单只是时钟那么简单,通过对它延伸和拓展,它还可以进行测量位移、速度、时间、以及定时和作开关的作用,通过举例对该设计稍加该进后测量布匹长度的例子,进一步让读者明确该时钟电路有别于普通的时钟电路。     

霍尔传感器在时钟电路中的应用

利用霍尔传感器,我设计出了一款时钟电路,而这款时钟电路不单单只是时钟那么简单,通过对它延伸和拓展,它还可以进行测量位移、速度、时间、以及定时和作开关的作用,通过举例对该设计稍加该进后测量布匹长度的例子,进一步让读者明确该时钟电路有别于普通的时钟电路.     

实现折叠共栅共源运放MST的时钟馈通频率补偿方法

该文基于二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种新型的时钟馈通频率补偿方法.该方法通过MOS电容引入时钟馈通进行频率补偿,无需对运放结构和参数进行调整.在Cadence ADE仿真环境下运用SMIC 0.35μm 2P3M Polyside Si CMOS模型参数,对折叠共源共栅放大器进行了模拟分析.结果表明,补偿后的运放实现了MST状态,并缩短了建立时间22.7%,提高了其响应速度.在0.5pF～2.5pF负载电容范围内,其建立时间近似线性变化,且对应每一负载电容值均达到MST状态.该方法可望应用于高速有源开关电容网络及其相关领域.     

Clock Feedthrough in CMOS Analog Transmission Gate Switches

An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these region and zone maps, the sign and relative magnitude of the clock feedthrough noise can be efficiently estimated for different signal levels. Placing the input voltage near half of the power supply voltage is a useful technique for minimizing clock feedthrough noise. A model of clock feedthrough noise as compared with SPICE simulations exhibits less than 3% error. This research was supported in part by the Semiconductor Research Corporation under Contract No. 99-TJ-687, the DARPA/ITO under AFRL Contract F29601-00-K-0182, grants from the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology—Electronic Imaging Systems and to the Microelectronics Design Center, and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak Company. Weize Xu received the B.S. degree from Nanjing University of Posts and Telecommunications, China in 1982, and the M.S. degrees from the University of Rhode Island in 1993, both in electrical engineering. Since 1997, he has been a senor research engineer and analog IC design specialist at Eastman Kodak Company. His research interests include high speed analog IC designs, pipelined A/D converter, low power switched capacitor circuit analysis and design, CMOS image sensor design, and analysis of noise in mixed signal ICs. He currently is a Ph.D candidate at the University of Rochester. Eby G. Friedman (S'78-M'79-SM'90-F'00) received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering. From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog IC's. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, the Director of the High Performance VLSI/IC Design and Analysis Laboratory, and the Director of the Center for Electronic Imaging Systems. He also enjoyed a sabbatical at the Technion—Israel Institute of Technology during the 2000/2001 academic year. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors and low power wireless communications. He is the author of more than 250 papers and book chapters, several patents, and the author or editor of seven books in the fields of high speed and low power CMOS design techniques, high speed interconnect, and the theory and application of synchronous clock distribution networks. Dr. Friedman is the Regional Editor of the Journal of Circuits, Systems, and Computers, a Member of the editorial boards of the Proceedings of the IEEE, Analog Integrated Circuits and Signal Processing microelectronics Journal, and Journal of VLSI Signal Processing, a Member of the Circuits and Systems (CAS) Society Board of Governors, and a Member of the technical program committee of a number of conferences. He previously was the past Editor-in-Chief of the IEEE Transactions on VLSI Systems, a Member of the editorial board of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Chair of the IEEE Transactions on VLSI Systems steering committee, CAS liaison to the Solid-State Circuits Society, Chair of the VLSI Systems and Applications CAS Technical Committee, Chair of the Electron Devices Chapter of the IEEE Rochester Section, Program or Technical chair of several IEEE conferences, Guest Editor of several special issues in a variety of journals, and a recipient of the Howard Hughes Masters and Doctoral Fellowships, an IBM University Research Award, an Outstanding IEEE Chapter Chairman Award, and a University of Rochester College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow.     

离散时间点格神经网络的开关电流电路实现

本文将原连续时间电压域点格神经网络（CNN）模型[1]映射到离散时间电流域，并采用开关电流（SI）技术来进行离散时间CNN的VLSI设计。给出了基本积木块的实现电路，并进行了连通片检测方面的简单应用研究。计算机仿真与理论结果相吻合，所得电路非常适合于用标准CMOS工艺集成，具有潜在的应用前景。     

雷达信号传输与处理及其模块化应用

本文评述雷达信号传输与处理模块化应用的需求和进展，应用模块化电路将使雷达功能大幅度提高，可靠性增强，大产量条件下成本降低。这对发展相控阵雷达作用尤为突出，对改造制式雷达也很有利。文中对雷达应用模块的多种形态（ＭＩＣ、ＭＨＭＩＣ、ＭＭＩＣ、ＭＣＭ等）进行各自特征和优势的多方面比较，微电子技术含量的不断提高，使雷达模块化应用更上一层楼。文中也简介了国内外部分产品的水平。     

模拟集成电路的发展动态

本文介绍了Ａ／Ｄ与Ｄ／Ａ转换器、超高速ＳＯＩ器件及电路、超高速双极电路、ＧｅＳｉ／Ｓｉ异质结器件和电路、智能功率等模拟集成电路的发展概况。     

音乐计时芯片乐音组合用分频器的设计

介绍铝栅CMOS高频音乐计时芯片中乐音组合用分频器的设计,电路具有频率高和负载能力强的特点,各级门延迟时间的分配和设计是关键。同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点,给出了平均延迟时间的设计结果,该设计已应用于高频时钟芯片的大批量生产中。     

IP环境下时钟同步网模型和指标的探讨

探讨和分析了时钟同步网指标和移动基站指标,结合本地网时间指标的分析,尝试给出了IP环境下同步网模型和指标分配。讨论的重点是时钟同步网,并在一定程度上论述了时间同步网。     

“信号分析与处理”课程教学改革实践

针对我校自动化学院电气工程及其自动化专业的实际情况,结合“对分课堂”的优点和可实施性以及新时代学生的特点,本教改项目将对分课堂教学模式应用到“信号分析与处理”课程体系中,提出了隔堂对分及当堂对分的教学模式。本项目分别针对两种模式进行了探索。实践证明,隔堂对分模式适合比较系统的知识点,学生课后进行内化吸收,下次课进行分组讨论;而当堂对分适合小而独立的知识点,学生带着问题当堂内化吸收,再进行分组讨论。这种新的教学模式都有效增强了学生的主动性,激发学生主动学习,其课堂效果显著。     

一种新的MOS结构量子化效应修正模型

从载流子在 MOS结构反型层内的经典分布和量子化后的子带结构出发 ,提出了经典的和量子化的表面有效态密度 (SL EDOS:Surface layer effective density- of- states)的概念。利用表面有效态密度的概念建立了经典理论框架和量子力学框架内的电荷分布模型。该模型包含了强反型区表面电势的变化对载流子浓度的影响 ,具有很高的计算效率和稳定性。在模型基础上 ,研究了量子化效应对反型层载流子浓度和表面电势的影响。     

基于高维空间最小生成树自适应覆盖模型的可拒绝分类算法

在高维空间样本较少的情况下,基于统计模型的可拒绝分类方法难以对样本分布的复杂几何形体构建合理的覆盖模型。为此,该文提出基于高维空间最小生成树自适应覆盖模型的可拒绝分类模型。该模型采用最小生成树刻画高维空间样本点分布,将图形的边作为新增虚拟样本以提供更好的同类样本分布描述。通过将同类相近样本划分到一个连通几何覆盖区域内,将不同类的相近样本归于不同几何覆盖区域内,实现对不同训练类的覆盖。为了克服因不合理虚拟样本造成分类器拒识性能的下降,引入自适应调整覆盖半径策略,实现对训练类的紧致性覆盖。对于测试样本,根据训练类覆盖边界便可对其作出拒识或者接受的处理,针对交叉覆盖的接受样本,再根据数据场策略确定其真正归属类别。实验结果表明本文方法合理有效。