An ultralow-power-consumption, high-speed, GaAs 256/258dual-modulus prescaler IC

A GaAs divide-by-256/258 dual-modulus static prescaler is described. The prescaler has a pulse-swallow counter-type architecture and quasi-differential switch flip-flops as its basic circuit architecture. For the input buffer circuit, a circuit called a source-coupled push-pull circuit has been developed that can generate high-frequency complementary signals from a single-phase signal at a low supply voltage. This IC operates at up to 14.5 GHz with a power consumption of 22 mW. The power consumption is less than 1/50 of the previously reported prescalers that can operate above 10 GHz     

An ultra-low-power-consumption high-speed GaAs quasi-differentialswitch flip-flop (QD-FF)

The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FFs. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers     

高速AlGaAs/GaAs HBT D-触发器和静态分频器

叙述了高速 Al Ga As/ Ga As HBT D-触发器和静态分频器的设计、制造和性能。用电流型逻辑和自对准工艺 ,D-触发器上升和下降时间都小于 80 ps,静态分频器在 0～ 8GHz频率范围功能正确     

Low power GaAs current-mode 1.2 Gb/s interchip interconnections

A new GaAs current-mode (CM) chip-to-chip interconnection circuit is presented that provides high signal transfer speed with a 50 Ω active termination and reduced input voltage swing. The power dissipation is shown to be 1/8 of an ECL I/O at the same data rate, 4 mW per pin, using a standard 2 V power supply. The driver-receiver operates with a current swing under 1 mA and provides a large noise margin     

High-speed GaAs SCFL monolithic integrated decision circuit for Gbit/s optical repeaters

A high-speed GaAs monolithic integrated decision circuit for Gbit/s optical repeaters, based on source coupled FET logic (SCFL) and designed to be completely ECL-compatible, has been developed. A clock phase margin of 150 degrees at 2 Gbit/s and IC yields of about 60% are achieved by using SCFL configuration. The developed IC operates stably from 10 to 60°C ambient temperature over a supply voltage fluctuation of more than 2 V.     

A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescalerusing a divide-by-2/3 synchronous counter

An extremely low-power CMOS/SIMOX divide-by-128/129 dual-modulus prescaler that operates at up to 1 GHz and dissipates 0.9 mW at a supply voltage of 1 V is presented. The prescaler is capable of 2-GHz performance with dissipation of 7.2 mW at 2 V. This superior performance is primarily achieved by using an advanced ultrathin-film CMOS/SIMOX process technology combined with a circuit configuration that uses a divide-by-2/3 synchronous counter. Using these same technologies, a single-chip CMOS phase-locked-loop (PLL) LSI that uses the developed prescaler was fabricated. It can operate at up to 2 GHz while dissipating only 8.4 mW at a supply voltage of 2 V. Even at a lower supply voltage of 1.2 V, 1-GHz operation can be obtained with a corresponding power consumption of 1.4 mW. These results indicate that the high-speed and very-low-power features of CMOS/SIMOX technology could have an important impact on the development of future personal communication systems     

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende...     

1.3 V supply voltage 38 GHz static frequency divider

An ultra-low supply voltage and low power dissipation fully static frequency InP SHBT divider operating at up to 38 GHz is reported. The fully differential parallel current switched configuration of D-latch maintains the speed advantages of CML circuits while allowing full functionality at a very low supply voltage. The frequency divider operates at up to 38 GHz at a single-ended input power of 0 dBm. The power dissipation of the toggled D-flip-flop is 8 mW at a power supply voltage of 1.3 V. The authors believe this is the lowest supply voltage for static frequency dividers around this frequency in any technology. This low power configuration is suitable for any digital integrated circuit.     

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fibercommunication systems using n-AlGaAs/i-InGaAs HJFET's

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-μm GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V     

A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBTtechnology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology     

10 GB/s bit-synchronizer circuit with automatic timing alignment byclock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs

A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V     

Compact low voltage four quadrant CMOS current multiplier

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 μm technology shows a linearity error lower than 0.9% for signal swings up to ±50 μA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz     

Low-power static frequency divider using an InP-based monolithic RTD/HBT technology

A low-power static frequency divider using an RTD/HBT MOnostable-BIstable transition Logic Element (MOBILE) scheme is proposed for the first time and operation of the circuit is demonstrated up to 20 GHz. The divided-by-two static frequency divider has been successfully implemented in an InP-based monolithic RTD/HBT IC technology. The number of devices used in the static frequency divider has been significantly reduced by using the proposed MOBILE scheme. The fabricated frequency divider operates at a clock frequency up to 20 GHz and dissipates d.c. power of 51 mW at a power supply of 3.3 V     

一种简化的光调制器驱动电路

在采用IC-CAP提取异质结双极晶体管器件的VBIC模型参数的基础上,设计出形式简洁的光调制器驱动电路．电路功耗仅为500mW,在2.5GHz信号下平均上升时间和下降时间（10%～90%）分别为84ps和56ps,输出电压摆幅2.6V．而FUJISTU公司的同类产品FMM3193VI平均上升时间和下降时间(20%～80%)为120ps,功耗为2.1W．     

A 15-Gb/s 2.4-V Optical Receiver Using a Ge-on-SOI Photodiode and a CMOS IC

We report the fastest (15 Gb/s) and lowest voltage (2.4V) all-silicon-based optical receiver to date. The receiver consists of a lateral, interdigitated, germanium-on-silicon-on-insulator (Ge-on-SOI) photodiode wire-bonded to a 0.13-$mu$m complementary metal–oxide–semiconductor (CMOS) receiver integrated circuit (IC). The photodiode has an external quantum efficiency of 52% at$lambda=850$nm and a dark current of 10 nA at$-$2 V. The small-signal transimpedance of the receiver is 91-dB$Omega$and the bandwidth is 6.6 GHz. At a bit-error rate of$10^-12$and$lambda=850$nm; the receiver exhibits sensitivities of$-$11.0,$-$9.6, and$-$7.4 dBm at 12.5, 14, and 15 Gb/s, respectively. The receiver operates error-free at rates up to 10 Gb/s with an IC supply voltage as low as 1.5 V and with a photodiode bias as low as 0.5 V. The power consumption is 3 to 7 mW/Gb/s. The Ge-on-SOI photodiode is well suited for integration with CMOS processing, raising the possibility of producing high-performance, low-voltage, monolithically integrated receivers based on this technology in the future.     

用于2.5Gbps千兆以太网发接器的时钟倍频器设计

提出了一种电荷泵锁相环电路实现的适用于 2 .5Gbps千兆以太网发接器要求的高速时钟倍频器的设计方法。为了获得高速时钟 ,设计中采用了双环路的 VCO结构 ,并且运用动态 D触发器来实现高速分频器。同时为了使得 PLL性能更加稳定 ,对电路作了进一步改进 :在 VCO的延迟单元中加了温度补偿部分 ,又采用箝位技术消除电荷泵中电荷重新分配引入的影响。运用 UMC0 .18μm,1.8V CMOS工艺模型 ,在 Cadence的环境下用 spectre S仿真器模拟 ;结果表明设计的时钟倍频电路对于不同的 PV T( P表示工艺变化引起的模型参数的变化 ,VT表示系统工作条件温度和电源电压的变化 )均能得到符合满足 2 .5Gbps千兆以太网发接器要求的时钟倍频信号 ,即使在最坏情况下电路也能保持很好的相位跟踪特性 ,输出静态相位误差平均为 50 ps,整个电路的功耗平均为 35m W。     

A single-chip GaAs RF transceiver for 1.9-GHz digital mobilecommunication systems

A 1.9-GHz single-chip GaAs RF transceiver has been successfully developed using a planar self-aligned gate FET suitable for low-cost and high-volume production. This IC includes a negative voltage generator for 3-V single voltage operation and a control logic circuit to control transmit and receive functions, together with RF front-end analog circuits-a power amplifier, an SPDT switch, two attenuators for transmit and receive modes, and a low-noise amplifier. The IC can deliver 22-dBm output power at 30% efficiency with 3-V single power supply, The new negative voltage generator operates with charge time of less than 200 ns, producing a low level of spurious outputs below -70 dBc through the power amplifier. The generator also suppresses gate-bias voltage deviations to within 0.05 V even when gate current of -144 μA flows. The IC incorporates a new interface circuit between the logic circuit and the switch which enables it to handle power outputs over 24 dBm with only an operating voltage of 3 V. This transceiver will be expected to enable size reductions in telephones for 1.9-GHz digital mobile communication systems     

A CMOS VCO Architecture Suitable for Sub-1 Volt High-Frequency (8.7–10 GHz) RF Applications

This paper proposes an LC-based oscillator structure which enables operation from a supply voltage as low as 0.85 V, while being suitable for high-frequency RF applications. Two VCO prototypes were fabricated in a standard 0.18 m CMOS process. The 8.7 GHz VCO operates from a supply voltage of 0.85 V, consumes 6 mW, and exhibits –100 dBc/Hz phase noise at 600 kHz offset. The 10 GHz prototype operates from a supply voltage of 1 V, consumes 9 mW, and has –98 dBc/Hz phase noise at 600 kHz offset. A tuning range of 400–450 MHz is achieved without using varactors.     

A low supply voltage high PSRR voltage reference in CMOS process

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm², a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm/°C and a standard deviation of 20 mV without trimming     

Low power integrated circuits for an implantable pulsed Doppler ultrasonic blood flowmeter

Describes two custom integrated circuits which were developed for an implantable pulsed Doppler ultrasonic blood flowmeter. Prime design goals were a minimum circuit volume, minimum power consumption, and operation at low supply voltages. The first of the two IC's performs system timing functions and produces the ultrasonic transmit burst. It can deliver up to 40 mW of peak output power at 50 percent efficiency and requires 3.7 mW standby power. The second IC, containing an RF amplifier, mixer and output amplifier, provides 54 dB conversion voltage gain for an 0.8 MHz bandwidth centered at 5.8 MHz, <3 dB noise figure, a dynamic range of 40 dB, and 1 /spl mu/s recovery time from a 1 V overload. This chip requires 2.7 mW power input.