Accurate RF electrical characterization of CSPs using MCM-D thin film technology

The thin film multilayer multichip module-deposited (MCM-D) technology of IMEC is used for characterising the RF electrical performance of two types of chip scale packages (CSPs). The measurement technique called MCM-on-package-on-MCM (MoPoM) enables accurate measurements and de-embedding in the gigahertz (GHz) range of frequencies. Wafer processing of the MCM-D technology allows for several design structures to be integrated on a single mask. The packages chosen are a 120-pin plastic ball grid array (PBGA) and an 80-pin polymer stud grid array (PSGA). Lumped element models extracted from measurements and three-dimensional simulations show good agreement with the measurements up to 6 GHz for the BGA and the PSGA. The electrical performance of the packages is compared at 1.8 GHz (GSM), 2.4 GHz (Bluetooth), and 5.2 GHz (HiperLAN) and at 5.2 GHz both the packages exhibit a return loss of lower than -10 dB and hence cannot be used in most cases without design improvement. We also show that the influence of encapsulant is significant while transmission line detuning due to the package is not significant at microwave frequencies. We also briefly mention about the crosstalk effects. We demonstrate the significant degradation in the performance of a 5.2 GHz MCM-D low noise amplifier (LNA) after packaging. A significant improvement in package performance is observed by conjugate matching the package interconnects.     

Benzocyclobutene as Substrate Material for Planar Millimeter-Wave Structures: Dielectric Characterization and Application

The application of benzocyclobutene (BCB) polymer as dielectric substrate material for millimeter-wave microstrip structures is investigated in this paper to face the problem of large losses due to standard dielectrics in the high microwave range. Dielectric properties of BCB are characterized from S-parameter measurements on a conductor-backed coplanar waveguide (CBCPW) using the polymer as substrate material. Excellent features, with a low loss tangent and a stable dielectric constant, are demonstrated within the measurement range from 11 GHz to 65 GHz. As a validation of BCB high frequency performances, the design and experimental characterization of a V-band array on BCB substrate is presented. Measurement results on both matching and radiation characteristics of the millimeter-wave array are discussed.     

Study of the self-alignment of no-flow underfill for micro-BGA assembly

As a concept to achieve high throughput low cost flip-chip assembly, a process development activity is underway, implementing next generation flip-chip processing based on large area underfill printing/dispensing, IC placement, and simultaneous solder interconnect reflow and underfill cure. The self-alignment of micro-BGA (ball grid array, BGA) package using flux and two types of no-flow underfill is discussed in this paper. A “rapid ramp” temperature profile is optimized for reflow of micro-BGA using no-flow underfill for self-aligning and soldering. The effect of bonding force on the self-alignment is also described. A SOFTEX real time X-ray inspection system was used to inspect samples to ensure the correct misalignment before reflow, and determine the residual displacement of solder joints after reflow. Cross-sections of the micro-BGA samples are taken using scanning electronic microscope. Our experimental results show that the self-alignment of micro-BGA using flux is very good even though the initial misalignment was greater than 50% from the pad center. When using no-flow underfill, the self-alignment is inferior to that of using flux. However, for a misalignment of no larger than 25% from the pad center, the package is also able to self-align with S1 no-flow underfill. However, when the misalignment is 37.5–50% from the pad center, there are 10–14% residual displacement after reflow. The reason is the underfill resistant force inhibiting the self-alignment of the package due to rapid increment of underfill viscosity during reflow. The self-alignment of micro-BGA package using no-flow underfill allows only <25% misalignment prior to the soldering. During assembling, although the bonding force does not influence on the self-alignment of no-flow underfill, a threshold bonding force is necessary to make all solder balls contact with PCB pads, for good soldering. The no-flow underfill is necessary to modify the fluxing/curing chemistry for overcoming the effect of tin metal salt produced during soldering on underfill curing, and for maintaining the low viscosity during soldering to help self-alignment.     

Signal integrity characterization of microwave XFP ASIC BGA package realized on low-K liquid crystal polymer (LCP) substrate

With the development of low-K nanometer devices, the need for compatible packaging material is ever increasing. Liquid crystal polymer (LCP) is emerging as a promising material for RF, microwave, and millimeter-wave packaging. Its coefficient of thermal expansion can be matched to that of low-K die to ensure mechanical reliability. This paper, for the first time, characterizes the electrical performance of a wire bonded application-specific integrated circuit (ASIC) ball grid array (BGA) package based on LCP substrate technology for application in 10 Gb/s small form factor pluggable module (XFP) optical communication systems. Specifically, it compares the electrical performance of LCP to that of traditionally used FR4/spl I.bar/epoxy (FR-4) and Polyimide (PI) substrate materials. Findings show that at 10 GHz, insertion loss was decreased as much as 31% and 15% compared to FR-4 and PI, respectively. In particular, mode conversion was decreased by 66% and 42% compared to FR-4 and PI, respectively. Time delay was decreased by 10 and 4 ps compared to FR-4 and PI. No significant differences in power, ground coupling, and simultaneously switching output (SSO) noise at 10 GHz were observed. Based on the package structure used in this study, it was concluded that LCP offers superior electrical performance compared to FR/spl I.bar/4, PI, and is qualified as next generation substrate material for high data rate XFP BGA packaging.     

Characterization of liquid crystal polymer for high frequency system-in-a-package applications

Liquid crystal polymer (LCP) is a promising substrate for electronics packaging. In this paper, the high frequency characteristics of LCP were investigated using a microstrip ring resonator to verify the possibility of applying the material in RF packaging. The relative dielectric constant and the loss tangent have been measured. The radiation loss of the ring is considered to accurately determine the loss tangent. A GaAs MMIC switch circuit was fabricated using LCP as substrate to demonstrate the application of this material for system-in-a-package. From the high frequency measurements, it is shown that LCP has low dielectric constant and low loss tangent in the frequency range from 1 GHz to 35 GHz. It is also found that LCP can be used in system-in-a-package applications.     

Dielectric constant, loss tangent, and surface resistance of PCB materials at K-band frequencies

This paper develops the theoretical approach and describes the design of a practical test rig for measuring the microwave parameters of unclad and laminated dielectric substrates. The test rig is based on a sapphire whispering-gallery resonator and allows the measurement of the following parameters: dielectric constant (epsiv) of the dielectric substrate in the range from 2 to 10, loss tangent (tandelta) of the dielectric substrate in the range from 10^-4 to 10^-2, and microwave losses of copper coating of the substrate in the range from 0.03 to 0.3 Omega. Measurements of numerous commonly used microwave printed-circuit-board materials were performed at frequencies between 30-40 GHz and over a temperature range of -50degC to +70degC     

Characterization of underfill materials for functional solderbumped flip chips on board applications

The curing conditions and material properties such as the TCE (thermal coefficient of expansion), T_g (glass transition temperature), flexural storage modulus, tangent delta, and moisture content of nine different underfill materials from three different vendors are measured. Their flow rate and the effect of moisture content on mechanical (shear) strength in solder bumped flip chips on organic substrate are also determined experimentally. Furthermore, their effects on the electrical performance (voltage) of functional flip chip devices on organic substrate are measured. Finally, a simple methodology is presented for the selection of underfills from the measurement results of these nine different underfill materials     

一种应用于12 GHz的AlN多层陶瓷外壳

以AlN材料为陶瓷基材,采用陶瓷绝缘子的射频传输端口结构及陶瓷焊球阵列封装形式,结合多层陶瓷加工工艺,设计并制备了一款可封装多个芯片的X波段AlN陶瓷外壳。采用应力仿真软件对外壳进行结构设计,利用电磁仿真软件对该外壳的射频端口进行仿真优化。采用微带线直接穿墙形式,设计了共面波导-带状线-共面波导的射频传输结构,并与陶瓷外壳进行一体化设计和制作。利用GSG探针对外壳样品进行测试,实测结果表明,在0~12 GHz频段内,外壳射频端口的插入损耗不小于-0.5 dB,回波损耗不大于-15 dB,AlN一体化外壳尺寸为10.25 mm×16.25 mm×4 mm,可广泛应用于高频高速信号一体化封装领域。     

Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L₁₈ orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.     

Effects of Glue on the Bend Performance of Flip Chip Packages

To combat reliability margin loss in ball grid array (BGA) packages specifically in mechanical shock and vibration testing, companies are exploring the possibility of using glue and complete underfill to mitigate risk to second-level interconnects (SLI). Though glue has been demonstrated to have a positive influence on SLI reliability margin, it can have adverse affects on the rest of the package such as substrate or first-level interconnects (FLI). This paper explains details on how glue modulates the overall reliability of the package. Finite-element modeling (FEM) along with low strain rate bend tests was done to prove the effect of glue on solder joint reliability. Further, shock testing was done to demonstrate how the glue modulates the shock performance. The improvement in SLI reliability was highly dependent on the choice of glue.      

Reliability assessment and hygroswelling modeling of FCBGA with no-flow underfill

In the flip-chip ball grid array (FCBGA) assembly process, no-flow underfill has the advantage over traditional capillary-flow underfill on shorter cycle time. Reliability tests are performed on both unmolded and molded FCBGA with three different types of no-flow underfill materials. The JEDEC Level-3 (JL3) moisture preconditioning, followed by reflow and pressure cooker test (PCT) is found to be a critical test for failures of underbump metallization (UBM) opening and underfill/die delamination. In this paper, various types of modeling techniques are applied to analyze the FCBGA-8×8 mm on moisture distribution, hygroswelling behavior, and thermomechanical stress. For moisture diffusion modeling, thermal-moisture analogy is used to calculate the degree of moisture saturation in the multi-material system of FCBGA. The local moisture concentration along the critical interface, e.g. die/underfill, is critical for delamination, because the moisture weakens the interfacial adhesion strength, generates internal vapor pressure during reflow, and induces tensile hygroswelling stress on UBM during PCT. The results of moisture distribution can be used as loading input for the subsequent hygroswelling modeling. The magnitude of hygroswelling stress acting on UBM is found to be greater than the thermal stress induced during reflow, both in tensile mode which may cause the UBM-opening failure. Underfill with lower saturated moisture concentration (C_sat) and coefficient of moisture expansion (CME) are found to induce lower UBM stress and has better reliability results. Molded package generally has higher stress level than unmolded package. Parametric studies are performed to study the effects of no-flow underfill materials, package type (molded vs. unmolded), die thickness, and substrate size on the stresses of UBM during reflow and PCT.     

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35 × 35 mm² packages with 15 mm die size and 45 × 45 mm² packages with 21 mm die size was selected. Target value for underfill properties has also been revised.     

Integrated circuit ceramic ball grid array package antenna

The recent advances in such highly integrated RF transceivers as radio system-on-chip and radio system-in-package have called for the parallel development of compact and efficient antennas. This paper addresses the development of a new type of dielectric chip antenna known as integrated circuit package antenna (ICPA) for highly integrated RF transceivers. A compact ICPA of this type has, for the first time, been designed and fabricated in a ceramic ball grid array (CBGA) package format. The novel ICPA, except economical advantage of mass production and automatic assembly, has potential benefit to the system-level board miniaturization and the system-level manufacturing facilitation. The simulated and measured antenna performance of the ICPA is presented. The effects of the different physical parts of the ICPA on the antenna performance are investigated. Results show that the ICPA achieved impedance bandwidth of 4.1% and radiation efficiency of 72%, and gain of 4.8 dBi at 5.715 GHz.     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

High performance package designs for a 1 GHz microprocessor

This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Integration of 0/1-Level Packaged RF-MEMS Devices on MCM-D at Millimeter-Wave Frequencies

This paper reports on the development and optimization of 0/1-level packaged coplanar waveguide (CPW) lines and radio-frequency microelectromechanical systems (RF-MEMS) switches up to millimeter-wave frequencies. The 0-level package consists of an on-chip cavity obtained by flip-chip mounting a capping chip over the RF-MEMS device using BenzoCyclobutene (BCB) as the bonding and sealing material. The 0-level coplanar RF feedthroughs are implemented using BCB as the dielectric; gold stud-bumps and thermocompression are used for realizing the 1-level package. The 0-level packaged switches have been flip-chip mounted on a multilayer thin-film interconnect substrate using a high-resistivity Si carrier with embedded passives and substrate cavities. The insertion loss of a single 0/1-level transition is below -0.15 dB at 50 GHz. The measured return loss of a 0/1-level packaged 50-Omega CPW line remains better than -19 dB up to 71 GHz and better than -15 dB up to 90 GHz. It is shown that the leak rate of BCB sealed cavities depends on the BCB width, and leak rates as low as 10^-11 mbar.l/s are measured for large BCB widths (> 800 mum), dropping to 10^-8 mbar.l/s for BCB widths of around 100 mum. Depending on the bonding conditions, shear strengths as high as 150 MPa are achieved.     

Residual compression in area array packages induced by underfill shrinkage

A non-linear finite element model is developed to investigate underfill shrinkage as a possible source for obtaining beneficial residual compression in solder grid array interconnects. The axisymmetrical model geometry consists of a unit cell of concentric cylinders, the inner with properties representative of solder and the outer with properties representative of underfill, having an outer radius of half the array pitch. The solder, which is assumed to be eutectic, is modeled as an elastic–plastic material that exhibits creep behavior. The elastic modulus and Poisson’s ratio of the underfill material, E_u and ν_u, as well as the percentage of unconstrained linear shrinkage, , are varied to determine the influence these parameters have on the final steady-state stresses in the solder connections. To represent the underfill materials in common use, E_u ranged from 0.5 to 8.0 GPa, ν_u ranged from 0.2 to 0.4, and ranged from 0.2% to 1.0%. Upon shrinkage of the underfill during curing, the model predicts that the interconnect initially experiences residual compression in the axial direction. Due to tension in the radial direction, however, creep strain causes the axial compressive stress to lessen until a state of hydrostatic stress is reached. For the underfill properties tested, all the residual, steady-state stresses were compressive. The magnitude of this compression is shown in graphical form as a function of E_u, ν_u, and . An analytical expression for estimating the magnitude of residual compression as a function of these underfill properties is also included. The potential effect of the residual compression on the fatigue life of a package is discussed in the context of a particular example.     

Material and process considerations for terahertz planar nanodevices

Using a two-dimensional ensemble Monte Carlo method, we have studied the capacitances in a planar nano-diode, called the self-switching device (SSD) that is based on an asymmetric nanochannel. We show that the terahertz (THz) response of the SSD can be affected by the dielectric constant and width of the insulating trenches that confine the nanochannel of the diode. The simulations reveal that the capacitive coupling over the insulating trenches has little influence on the device RF properties below 100 GHz, but significantly affects the device performance around and beyond 1 THz. We show that the capacitance is more sensitive to the dielectric constant of the substrate but is relatively less sensitive to the width of the insulating trench or the dielectric constant of the infill material in the insulating trenches. This differs significantly from a conventional capacitor with two parallel plates. The findings in this work provide useful implications in optimizing the material and lithography parameters of such and similar nanodevices for THz applications.     

Modeling of lead-frame plastic CSPs for accurate prediction oftheir low-pass filter effects on RFICs

This paper presents a direct extraction method to construct the electrical models of lead-frame plastic chip scale packages for RF integrated circuits (RFICs) from the measured S-parameters. To evaluate the package effects on the reciprocal passive components, the insertion and return losses for an on-chip 50-Ω microstrip line housed in a 32-pin bump chip carrier (BCC) package were analyzed based on the established package model. Excellent agreement with measurement has been found up to 15 GHz. When applied to the nonreciprocal active components, the gain variations for a heterojunction-bipolar-transistor array housed in an 8-pin BCC package have also been successfully predicted up to 22 GHz. Both cases have demonstrated that the package acts as a low-pass filter to cause a sharp cutoff for the RFIC components above a certain frequency