共查询到20条相似文献,搜索用时 828 毫秒
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为了提高功率器件结终端击穿电压,节约芯片面积,设计了一款700 V VDMOSFET结终端结构。在不增加额外工艺步骤和掩膜的前提下,该结构采用场限环-场板联合结终端技术,通过调整结终端场限环和场板的结构参数,在151μm的有效终端长度上达到了772 V的击穿电压,表面电场分布相对均匀且最大表面场强为2.27×105V/cm,小于工业界判断器件击穿场强标准(2.5×105 V/cm)。在保证相同的击穿电压下,比其他文献中同类结终端结构节约面积26%,实现了耐压和可靠性的要求,提高了结终端面积的利用效率。 相似文献
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对常用的场限环(FLR)和正、负斜角终端结构的耐压机理进行了简要分析,讨论了其结构参数的优化方法.基于GTR台面终端结构,在功率MOSFET中引入了一种类似的沟槽负斜角终端结构.利用1SE软件对其耐压机理和击穿特性进行了模拟与分析.结果表明,采用沟槽负斜角终端结构会使功率MOSFET的耐压达到其平行平面结击穿电压的92... 相似文献
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介绍了高压空间调制结终端扩展(SM-JTE)结构及其优势。结合实际的MOSFET工艺和已有的理论模型,定义了全新的4H-SiC器件TCAD仿真模型参数。首次提出了确定SM-JTE最优长度的方法。基于SM-JTE结构的4H-SiC器件具有优良的击穿特性。SM-JTE结构的长度为230 μm时,SM-JTE的击穿电压可以达到16 kV。针对界面电荷对击穿特性的影响进行了系统仿真研究。仿真结果表明,正界面电荷相比负界面电荷对击穿电压的影响更大,且界面态电荷会引起击穿电压明显下降。该SM-JTE结构可以采用更短的结终端,在同样尺寸的芯片上能制作更多的器件,从而提高生产效率,降低器件成本。 相似文献
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为了改善超结MOSFET功率器件的终端击穿特性,提出了一种平面结终端技术,应用柱坐标下的泊松方程证明了这种技术的可行性。提出了超结功率器件终端技术的工艺实现方法并分析了终端结构的电压特性,使用这种超结终端技术仿真得到了一个600V的Coolmos。利用2维仿真软件Medici讨论了终端p柱的数量和宽度因素对击穿电压和表面电场的影响。结果发现,采用变间距的超结结构本身就可以很好地实现超结MOSFET功率器件的终端。 相似文献
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利用二维半导体工艺及器件模拟工具,从结掺杂浓度、P阱与P环间距、P环尺寸控制3个方面分析了半绝缘多晶硅终端结构的击穿电压,提出了应用于1 200 V沟槽栅场截止型IGBT的终端解决方案。从结的深度和终端长度两方面,将SIPOS终端技术与标准的场环场板终端技术进行了对比。结果表明,采用SIPOS终端结构并结合降低表面场技术,使得终端尺寸有效减小了58%,并且,采用SIPOS技术的终端区域击穿电压受结深的影响较小,有利于实际制造工艺的控制和IGBT器件稳定性的提升。 相似文献
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《Electron Devices, IEEE Transactions on》1966,13(11):763-770
Current constriction in a p-n junction under a thermal mode of breakdown is analyzed and expressions for terminal voltage and radius of constriction are derived for silicon devices. The values predicted by this model are of the same order as those observed for transistors under second breakdown; it is proposed that second breakdown in transistors is a thermal mode of breakdown which inevitably follows if energy dissipated in the avalanche mode of breakdown is large enough to increase the temperature of some portion of the junction to the intrinsic or turnover temperature of the junction. 相似文献
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采用场极板结终端技术提高LDMOS击穿电压,借助二维器件仿真器MEDICI软件对基于体硅CMOS工艺500V高压的n-LDMOS器件结构和主要掺杂参数进行优化,确定漂移区的掺杂浓度(ND)、结深(Xj)和长度(LD)。对多晶硅场极板和两层金属场极板的结构参数进行模拟和分析,在不增加工艺复杂度的情况下,设计一种新型的具有两层金属场极板结构的500Vn-LDMOS。模拟结果表明,双层金属场极板结构比无金属场极板结构LDMOS的击穿电压提高了12%,而这两种结构LDMOS的比导通电阻(RS)基本一致。 相似文献
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Yoshimi M. Takahashi M. Wada T. Kato K. Kambayashi S. Kemmochi M. Natori K. 《Electron Devices, IEEE Transactions on》1990,37(9):2015-2021
The drain breakdown phenomenon in ultra-thin-film (silicon-on-insulator) SOI MOSFETs has been studied. Two-dimensional simulation revealed that the thinning of the SOI film brings about an increase in the drain electric field due to the two-dimensional effect, causing a significant lowering in the drain breakdown voltage, as has been commonly seen in ultra-thin-film SOI MOSFETs. The simulation also showed that the lowered drain breakdown voltage recovered almost to its original value when the drain SOI thickness was restored, suggesting that the drain structure, rather than the source, plays a major role in determining the drain breakdown voltage. Experiments using an asymmetric device structure supported this hypothesis, showing that the breakdown voltage was mostly dependent on the drain structure, the initial potential barrier height at the source-SOI-body junction being only a minor factor. Transient simulation was also carried out to investigate the detailed breakdown process, showing that holes accumulate near the source-SOI-body junction at a high drain bias, eventually forward-biasing the junction. These results indicate that a careful drain design and/or proper choice of the SOI thickness as well as the supply voltage are quite important for realizing high performance of ultra-thin-film SOI MOSFETs 相似文献
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《Microelectronics Reliability》2014,54(12):2704-2716
The reduction of breakdown voltage (BV) influenced by high voltage interconnection (HVI) is a key problem in power integrated circuit, which essentially is that the modulation of electric field distribution at the device surface caused by HVI. In this paper, we review the developments of the methods to shield HVI including thick insulating film technology, field reduction layer technology, field plate technology and self-shielding technology. The four kinds of HVI technologies prevent BV degradation from the introduced adverse charge induced by interconnections in different ways. Thick insulting film technology increases the distance between the HVI and surface of silicon. Field reduction layer technology uses additional doping layers with optimized impurity concentration to enhance the depletion of the drift region under HVI. Field plate technology shields the influence of HVI with various field plate structures. Self-shielding technology makes HVI avoid crossing over high voltage junction terminal (HVJT), thus no additional shielding structure is needed. The divided reduced surface field (RESURF) technology solves the leakage current in the self-shielding structure. 相似文献
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借助半导体仿真软件Silvaco,仿真一种具有结终端扩展(JTE)结构的碳化硅(SiC)肖特基二极管(SBD)。其机理是通过JTE结构降低肖特基结边缘的电场集中效应,从而优化肖特基二极管的反向耐压能力。研究JTE区深度、宽度及掺杂浓度对碳化硅肖特基二极管的反向耐压的影响。通过优化结终端结构的结构参数使碳化硅肖特基二极管的反向耐压特性达到更好的性能要求。 相似文献
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Chen J.J. Gao G.-B. Chyi J.-I. Morkoc H. 《Electron Devices, IEEE Transactions on》1989,36(10):2165-2172
Avalanche breakdown behavior at the collector junction of the GaAs/AlGaAs HBT (heterojunction bipolar transistor) has been studied. Junction breakdown characteristics displaying hard breakdown, soft breakdown, and negative resistance breakdown behavior were observed and are interpreted by analysis of localized microplasma effects, uniform microplasma-free behavior, and associated current gain measurements. Light emission from the collector-base junction of the GaAs/AlGaAs HBT was observed and used to investigate breakdown uniformity. Using a simple punchthrough breakdown model, the theoretical breakdown curves at different collector doping concentrations and thicknesses were computed and found to be in agreement with maximum breakdown voltages measured from devices displaying the most uniform junction breakdown. The serious current gain degradation of GaAs/AlGaAs HBTs at low current densities was analyzed in connection with the measurement of a large collector-emitter breakdown voltage. The unexpected functional relationship between the collector-emitter breakdown voltage and collector-base breakdown voltage is explained by the absence of a hole-feedback effect for devices not exhibiting transistor action 相似文献
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Maximum surface and bulk electric fields at breakdown for planar and beveled devices 总被引:3,自引:0,他引:3
《Electron Devices, IEEE Transactions on》1978,25(10):1266-1270
Techniques previously presented for predicting breakdown voltage on planar devices with and without a field ring and in negative beveled devices are greatly extended so that the peak bulk and surface electric fields at breakdown can now be predicted. In addition, new techniques are described which for the first time allow the peak bulk and surface electric fields to be predicted for all positive and double positive beveled devices. Using this paper it becomes possible to predict peak bulk and surface electric fields as well as breakdown voltage for all planar and beveled devices. This is accomplished by the use or normalization procedures which allow dependencies on the substrate doping, junction depth, surface concentration, junction curvature, and bevel angle to be reduced to a single dependence. It is shown that the positive bevel is most effective in reducing surface electric fields with the negative bevel, double positive bevel, and the field ring for planar devices in decreasing order of effectiveness. 相似文献