A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-heldterminals

The modulator IC is a mixed analog/digital transceiver component in a chip set that is designed for the hand-held terminals of the pan-European 900-MHz Groupe Special Mobile (GSM) digital cellular radio network. The concept of the radio-frequency environment in which the circuit is used is explained, focusing on the differences in existing systems. The architecture and different functions of the modulator circuit and details of the digital and analog processing in the transmission mode are discussed. The receiving mode, which is mostly based on analog processing, is highlighted. The device generates Gaussian minimum-shift-keying (GMSK) modulation and converts the received signal to 8-b words after filtering. The modulator IC uses digital waveform generation and a quadrature signal representation. This device is implemented in a 1.5-μm CMOS technology. The power consumption is less than 35 mW from a 5-V supply     

High Average-Efficiency Multimode RF Transmitter Using a Hybrid Quadrature Polar Modulator

This paper presents a hybrid quadrature polar modulator (HQPM) to drive the power amplifier (PA) highly efficiently in a wireless RF transmitter required for multimode operation. For enhancing the transmit efficiency, a switching-mode PA realized as Class-E design is used in the transmitter. The HQPM consists of a quadrature modulator for processing the RF modulated carrier and a Class-S modulator for processing the supply-voltage signal. The quadrature modulator and the Class-S modulator deliver the output signals with proportional envelope variation before being inserted into the RF-input terminal and the supply-voltage terminal of a Class-E PA, respectively, causing the double envelope modulation to distort the modulated RF signal at the PA output. Therefore, a digital predistorter is embedded in the HQPM for compensation. The proposed HQPM-based transmitter can help reducing the average dc and input RF powers and the output feedthrough levels so as to enhance power added efficiency and adjacent channel power rejection remarkably.     

A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter

In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpolation chain for data streams and four digital frequency synthesizer/modulators, which are based on a coordinate rotation digital computer (CORDIC) vector rotation algorithm. The interpolation chain consists of a root-raised cosine pulse shaping filter and three half-band filters for image filtering. The modulated carriers are combined to form a multicarrier WCDMA signal. The SINC-attenuation effect of a digital/analog (D/A) converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter, which is integrated on the same silicon chip. The modulator is implemented with a 0.35-mum BiCMOS process with CMOS transistors only     

A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

基于AD9957的数字正交调制器设计

数字正交调制器是软件无线电体系中关键组成部分,小型化、通用化、参数可配置是数字正交调制器发展需求。基于ADI公司正交上变频器AD9957芯片特点,提出了一种基于AD9957的通用数字正交调制器的设计方案,具有参数可变、硬件结构简单、集成度高、数字成形的特点。给出了核心硬件电路框图,进行了设计实现和测试,与参考数据进行了对比,实测结果与参考数据基本一致。     

基于软件无线电的DS/DQPSK调制解调器

一种基于软件无线电的数字DS/DQPSK调制和解扩解调器的FPGA实现方案。采用了调制前的基带成形处理、正交调制、数字匹配滤波解扩和延时差分解调等技术,直接对中频模拟已调信号进行带通采样,然后使用FPGA进行数字信号处理,完成基带数据的解扩解调以及基带时钟提取,不需要进行数字下变频,也不需要进行伪随机码同步捕获和载波提取,简单易行,具有一定的新意和较高的实用价值。     

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm².     

A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speedwireless applications [LANs]

A DS-CDMA demodulator uses analog sampled-data signal processing to achieve a 75-mW power dissipation and a 128-MS/s processing rate in a 1.2-μm double-metal double-poly CMOS process. To demodulate the signal, a low-power passive correlation technique is introduced that eliminates the integrating opamp with its associated power and settling time overhead. In a prototype demodulator, six 64-chip correlators recover the 2-Mb/s data stream from the doubly modulated [pseudorandom noise (PN) and Walsh] quadrature input signal. An on-chip 10-b pipelined ADC sampling at 8 MS/s follows the analog correlation to permit digital implementation of the acquisition and tracking algorithms     

A general purpose differential digital modulator implementationincorporating a direct digital synthesis method

A highly versatile digital modulator that uses a direct digital synthesis method to perform signal modulation is described. In contrast to the customary methods of implementing I-Q modulation schemes utilizing in-phase and quadrature branches, this design approach is based on directly accessing many of the digitally stored carrier modulating symbols according to the information bearing input signals. Apart from the digital-to-analog converter, all the previous stages are digital. To demonstrate the concept, a differential 16-QAM modulator was implemented. The technique lends itself to VLSI implementation. It can be considered as a digital implementation of a digital modulator     

基于DDS的任意频谱信号重构与数字正交调制方法

任意频谱信号产生方法是将功率谱转换为矢量频谱,再经傅立叶反变换,对得到的多个时域数据序列进行加窗、搭接得到一个长的时间序列,用该序列去逼近任意频谱信号对应的时域无限长序列,最后经过数字正交调制重构出任意频谱信号。计算机仿真分析表明,本文方法的理论重构精度达80dB以上,通过直接数字频率合成技术（DDS）实现的数字正交调制器的实际输出信噪比达65dB以上。     

Research on Properties of Devices for Shaping and Processing of Signals Based on Amplitude Modulation of Many Components

Devices for shaping and processing of signals based on known varieties of digital amplitude-phase modulation are considered. Their disadvantages are exposed during realization of modulation and demodulation of the signals that are characterized by non-rectangular signal constellations. There are explored properties of devices for shaping and processing of signals based on a new variety of signal modulation, namely amplitude modulation of many components (AMMC). The results of carried out researches show that advantages of proposed AMMC modulator are simplification of phase modulated or amplitude-phase modulated signal shaping, in particular AMMC signal shaping, and improve of modulator internal interference protection. Advantages of AMMC demodulator are simplification of phase modulated or amplitude-phase modulated signal processing, in particularAMMC signal processing, and improve of demodulator internal interference and zero drift protection at its practical realization. The proposed AMMC modulator and demodulator can be applied for shaping and processing of signals based on known and new varieties of amplitude-phase modulation.     

A fourth-order bandpass sigma-delta modulator

The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta (ΣΔ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio     

A 1.9-GHz-band GaAs direct-quadrature modulator IC with a phaseshifter

A 1.9-GHz-band direct-quadrature modulator IC has been successfully developed for digital portable telephone use. In the 1.9-GHz high-frequency band, both image and carrier rejections as low as -40 dBc have been obtained with a low-power dissipation of 110 mW at a single power supply of 3.1 V, corresponding to a phase error below 1.1. In order to reduce undesired sideband spectral components required for digital modulation, a newly developed circuit configuration that combines a quadrature phase shifter with drivers for amplitude imbalance compensation and makes spectrum efficiency and low-power dissipation possible is used. The modulator IC may be used in enhanced digital mobile radiocommunication systems such as digital portable telephones     

Mixed Cartesian feedback for Zero-IF WCDMA transmitter

In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA zero-intermediate frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback I/Q demodulator, and a digital stage adjusting the phase rotation around the loop. The whole system consumes 500 and 2.94 mW, respectively, for the analog and the digital part. System level simulation gave a maximum improvement of 35 dBc at 5 MHz from the carrier for the W-CDMA signal.     

基于FPGA的北斗QPSK调制实现与解调验证

为研制北斗卫星导航模拟信号源,设计实现了北斗QPSK信号调制器。文中在分析了北斗卫星导航系统B1频段信号的正交相移键控调制信号的基础上,基于软件无线电的思想,在FPGA 硬件平台上实现了QPSK信号调制器,通过功率谱测试,QPSK解调和简单串口信息传输,验证了调制解调硬件单元的正确性。     

A 56 mW Continuous-Time Quadrature Cascaded Σ∆ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.     

Adaptive compensation for imbalance and offset losses in directconversion transceivers

The current interest in linear modulation and multilevel signals has resulted in an emphasis on DSP implementations to achieve precision signal manipulation. However, most transceivers, and direct conversion designs in particular, rely on analog implementations of the quadrature modulator and demodulator, thereby sacrificing much of the precision gained through DSP. The present paper focuses on the three principal impairments of analog quadrature modulators and demodulators: gain imbalance, phase imbalance, and DC offset. The paper contains three main contributions. First is an analysis and quantitative assessment of the losses-primarily a degraded BER and out-of-band power in the transmitted signal-due to imbalances and offsets. The second contribution is an adaptive compensation technique for the quadrature modulator at the transmitter, and the third is a compensation technique for the quadrature demodulator at the receiver. Both compensation methods converge quickly and present only a modest computational load     

低功耗Sigma Delta调制器的建模与设计

针对Sigma Delta ADC在实现高精度的同时如何降低系统功耗这一问题,通过进行建模分析,得出满足精度需求的最低性能指标。并对二阶Sigma Delta调制器的非理想因素进行数学建模分析,在满足ADC精度的同时对ADC组成模块的最低性能指标进行分配,利用SDtoolbox进行仿真验证。基于CSMC 0.5 μmCMOS工艺,在5 V电源电压下,对调制器进行了电路级设计。结果显示在模块最低性能时,调制器输出信号的带内信噪比为835 dB,总功耗为18 mW。     

Baseband Digital Predistorter with Quadrature Error Correction

In this article simulation and measurement results of a FPGA implementation of a baseband digital complex gain predistorter with a quadrature modulator and demodulation error correction circuits are presented. Four different methods for finding the quadrature error correction values are compared and the effect of quadrature errors to predistortion is discussed. A 50 dB three stage power amplifier chain with an analog quadrature modulator and demodulator was used in the measurements as the device to be predistorted. The signal used in the measurements and simulations was a 30 dBm 18 kHz 16-QAM signal at 400 MHz carrier frequency. In the measurements 15 dB reduction in 3rd order nonlinearity was achieved. The usage of quadrature error correction reduced the adjacent channel power by 9 dB. Ilari Teikari was born in Tampere, Finland, in 1978. He received the M.Sc. (tech.) degree from Helsinki University of Technology (HUT), Helsinki, Finland, in 2002. He is currently working toward D.Sc. (tech) degree in the electronic circuit design laboratory, HUT. His current research intrests are in the area of power amplifier linearization methods and digital circuit design. Jouko Vankka was born in Helsinki, Finland, in 1965. He received the M.S. and Ph.D. degrees in electrical engineering from Helsinki University of Technology (HUT) in 1991 and 2000, respectively. Since 1995, he has been with the Electronic Circuit Design Laboratory, HUT. His research interests include VLSI architectures and mixed-signal integrated circuits for communication applications. Kari A. I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from Helsinki University of Technology, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, in Heverlee, Belgium, in 1987. From 1982 to 1984 he was employed as assistant at Helsinki University of Technology and as research assistant at the Technical Research Center of Finland. From 1984 to 1987 he was a research assistant at the E.S.A.T. Laboratory of the Katholieke Universiteit Leuven, enjoying also a temporary grant of the Academy of Finland. Since 1988 he has been with the Electronic Circuit Design Laboratory, Helsinki University of Technology, as senior assistant (1988–1990), and the director of the Integrated Circuit Design Unit of the Microelectronics Center (1990–1993). He was on leave of absence the academic year 1992–1993, acting as R&D manager in Fincitec Inc., Finland. From 1993 to 1996 he has been an associate professor, and since 1997 a full professor at the Faculty of Electrical Engineering and Telecommunications, Helsinki University of Technology. He became the Head of Electronic Circuit Design Laboratory year 1998. From 1997 to 1999 he was an associate editor of IEEE Transactions on Circuits and Systems I. He has been a guest editor for IEEE Journal of Solid-State Circuits and the Technical Program Committee Chairman for European Solid-State Circuits Conference year 2000. He has been awarded the Beatrice Winner Award in ISSCC'02 Conference year 2002. He specializes in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. He is author or co-author over a hundred and fifty international and national conference and journal publications on analog integrated circuits. He has several patents on analog integrated circuits.