一种NCITS 256协议超高频无源射频识别标签

设计了一种符合NCITS 256协议的无源超高频射频识别标签.标签携带2kbit的标准商用EEPROM.在读卡器发射功率为915MHz 4W EIRP的情况下,芯片的读距离为1.5m,写距离为0.3m.芯片在SMIC 0.18μm EEPROM CMOS工艺下流片实现,面积为1mm×1mm.标签使用Dickson倍压电路从读卡器发射的电磁波中提取能量.Dickson倍压电路使用肖特基管实现,转换效率为25%.     

低压低功耗无源UHF RFID标签芯片模拟前端电路的设计

本文从设计符合EPCTM C1G2协议的超高频无源射频识别标签芯片的角度出发,对RFID标签芯片模拟前端电路进行设计.通过对各个关键电路的功耗与电源进行优化,实现了一个符合协议要求的低电压、低功耗的超高频无源RFID标签芯片的模拟前端.该UHF RFID标签模拟前端设计采用SMIC 0.18 μm EEPROM CMOS工艺库.仿真结果表明,标签芯片模拟前端的整体功耗控制在2.5 μW以下,工作电源可低至1 V,更好地满足了超高频无源射频识别标签芯片应用需求.     

应用于低频无源RFID的低成本2 kbit EEPROM

基于350 nm 2-poly 3-metal EEPROM工艺，设计了一种应用于低频无源RFID的低成本2 kbit EEPROM存储器。在保证存储容量能满足大多数使用场景的情况下，通过优化Dickson电荷泵和读出电路的结构，实现电路版图面积的最小化，从而对整体电路实现低成本设计。优化后的Dickson电荷泵能实现10μs内从3.3 V到16 V的稳定升压，且功耗为334μW;读出电路基于检测NCG器件阈值电压的方式实现存储逻辑值的判别，该方法不需要能提供高精度电流的基准电路和具有高增益的灵敏放大器，有效降低了整体电路的面积。低成本2 kbit EEPROM的工作电压为3.3 V,能实现32位并行输入和1位串行输出，芯片总面积仅为0.14 mm²,有效降低了低频无源RFID设计复杂度和制造成本。     

无源UHF RFID芯片中低功耗基带处理器的设计

对UHF RFID标签芯片的数字基带处理器结构及工作原理进行了分析。该基带处理器兼容ISO18000-6C协议。采用一系列先进的低功耗技术,如门控时钟技术、减小工作电压、降低时钟频率等,以降低无源射频识别标签的功耗。整个标签芯片采用TSMC 0.18μm 1P5M嵌入式EEPROM混合CMOS工艺实现。测试结果表明,该芯片正常工作的最低电压仅为1 V,平均电流为6.8μA,功耗为6.8μW,面积仅为150μm×690μm。     

一种低功耗高频RFID标签芯片基带控制器

设计了一款应用于高频射频识别标签芯片的基带控制器。该基带控制器符合ISO15693标准协议,满足无源射频识别标签的低成本、低功耗的需求。详细论述了解码电路、命令响应模块及状态机、数据组织模块等关键电路的设计。芯片采用中芯国际0.35μm2P3M嵌入式EEPROM的混合信号CMOS工艺实现,基带控制器的Core面积仅为0.23mm2,功耗低至66.8μW。     

一种小型UHF RFID抗金属标签天线的设计

针对射频识别标签天线小型化、抗金属环境的实际需求,提出了一种可应用于金属环境的超高频射频识别标签天线.通过在矩形贴片上开槽来实现小型化,天线总尺寸为56 mm×50 mm×1.6 mm.通过改变槽的尺寸调节标签天线的输入阻抗,结合等效电路图分析抗金属标签天线的设计过程,从而方便地实现与标签芯片的共轭匹配.实验结果表明,实测和仿真结果比较吻合,标签阻抗匹配良好,实测最大读取距离达3.1m.与其他标签天线相比,该天线具有结构简单、成本低、易于实现和读取距离远等优势.     

一种13.56MHz无源射频识别模拟前端的设计

提出了一种基于ISO/IEC18000-3协议的高频13.56MHz射频识别(RFID)标签芯片的模拟前端电路结构,采用Chartered 0.35μm EEPROM工艺进行流片验证。该芯片实现了无源RFID标签芯片通信时所需的整流、稳压供电、时钟恢复、信号解调以及副载波调制的全部功能。     

基于RC522的RFID读卡器电路设计实现

设计一种基于MF RC522的射频读卡器,工作频率为13.56MHz。电路控制的核心部分采用STM32单片机实现,射频信号发送与接收采用集成射频读写芯片MF RC522完成,RS232串口实现了读卡器与上位机的通信连接,测量了周围无金属物时的最大读卡距离为60mm,高于MF RC522数据手册中给定的最大典型操作距离50mm,达到设计要求。     

一种PMOS管传输型高效电荷泵电路设计

设计了一种基于传统Dickson结构的PMOS管传输型电荷泵电路。电路通过衬底电位跟随器实现PMOS管传输,避免了传输过程中阈值电压损失;通过电阻分压反馈网络、控制振荡器输出达到稳压的目的;在电荷泵不工作时,各个子电路关断,实现低功耗设计。仿真结果表明,电路效率高,上电时间短,纹波小;采用SMIC 0.18μm工艺流片,电路达到设计要求,输出高压稳定,驱动能力强,在1M EEPROM电路芯片中得到实际应用。     

一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路

提出了一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路.通过引入一个使用亚阈值技术的基准源,电路实现了温度补偿,从而使得系统时钟在～40～100℃的范围内保持稳定.在模块设计中,提出了一些新的电路结构来降低系统功耗,其中包括一种零静态功耗的上电复位电路和一种新的稳压电路.该射频/模拟前端电路采用不带肖特基二极管0.18μm CMOS EEP-ROM工艺流片实现,它与数字基带、EEPROM一起实现了一个完整的标签芯片.测试结果表明,该芯片的最低电源电压要求为0.75V.在该最低电压下,射频/模拟前端电路的总电流为4.6μA.     

A versatile stacked storage capacitor on FLOTOX cell for megabitNVRAM's

A versatile stacked storage capacitor on FLOTOX (SCF) structure is proposed for a megabit nonvolatile DRAM (NV-DRAM) cell that has all the features required for NVRAMs. The SCF structure realizes a 30.94-μm ² NV-DRAM cell with 0.8-μm design rules and allows an innovative flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb original data in DRAM or EEPROM. This store operation is completed in less than 10 ms. The single cell shows excellent reliability such as store endurance greater than 10⁶ cycles and EEPROM data retention in excess of 10 years under high storage temperatures of 150°C and DRAM write operation at 85°C. The SCF cell has been successfully implemented into the 1 Mb NVRAM     

An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control

This paper presents an EEPROM programming controller imbedded in a passive UHF RFID transponder. A 14 V programming voltage is generated and regulated for a 224-bit EEPROM memory array from a rectified voltage supply of 2–3 V. A gated clock regulation loop is proposed to keep the programming voltage constant over a wide range of received RF input power, in order to improve the write–erase endurance of the memory. A current surge control scheme is proposed to allow the EEPROM programming voltage ramping in steps, therefore, preventing the collapse of the rectified supply in the remotely powered transponder. Also presented is a nano-power switched bandgap reference to reduce die area through the reduction of M$Omega$ resistors needed for nano-power operation. Measurement results show that a 0.35 $mu{hbox {m}}$ CMOS transponder IC provides a stable EEPROM programming voltage which varies less than 8% over a large 30 dB input power range while consuming 7 $mu{hbox{W}}$. The EEPROM programming controller occupies 0.092 ${hbox {mm}}^{2}$ die area.      

A new type of low power read circuit in EEPROM for UHF RFID

A novel low power read circuit without reference in 1 k-bits electrically erasable and programmable (EEPROM) for UHF RFID is designed and implemented in SMIC 0.18 μm EEPROM process. The read power consumption is optimized using a pre-charge sense amplifier. To improve the performance of the read circuit, a self-detect circuit, a read control logic and a feedback scheme are adopted, combined with a special time sequence. For a power supply voltage of 1 V, an average power consumption of 1.6 μA for the read operation of the EEPROM can be achieved when the read clock frequency is 640 kHz. What is more, with a 110 °C temperature change, the read power consumption variation is as low as 12%. The die size of the EEPROM is 0.15 mm², where the read circuit occupies 0.0125 mm².     

Low‐Power 512‐Bit EEPROM Designed for UHF RFID Tag Chip

In this paper, the design of a low‐power 512‐bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low‐power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage‐up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 μm EEPROM process. Power dissipation is 32.78 μW in the read cycle and 78.05 μW in the write cycle. The layout size is 449.3 μm × 480.67 μm.     

一种内嵌EEPROM的双电源数字电位计设计

设计了一种基于嵌入式EEPROM工艺的双电源数字电位计。通过两线的I2C总线来控制电路内部EEPROM单元,调节数字电位计的输出电阻或电压。电路采用正负电源供电,同时集成了两路256个抽头可变电位计输出。由于内部集成了EEPROM单元,当电路突然掉电后依然保存抽头设置信息,重新上电后,自动恢复到掉电前电阻抽头的设定位置。该电路采用SMIC 0.18μm EEPROM工艺设计,版图面积为6.76 mm2,采用Hsim对整个电路进行仿真。仿真和测试结果表明,该电位计电路的整体非线性小于±1 LSB,级间非线性小于±0.5 LSB,输出电阻温度系数小于±100×10-6/℃,EEPROM上电恢复时间小于5 ms,可广泛应用于控制系统、参数调整和信号处理领域。     

A low-power 1 MHz, 25 mW 12-bit time-interleaved analog-to-digitalconverter

A 12-bit 1 Msample/s 25 mW analog-to-digital converter was designed. Linearity, offset, and gain errors of less than 1/2 LSB have been achieved using an EEPROM memory trimming scheme. The EEPROM memory array, programmed during testing, continuously drives a correction digital-to-analog converter (DAC) with code dependent correction factors. The analog-to-digital converter (ADC) uses a time-interleaved multistep architecture consisting of two banks of comparator arrays sharing a common reference ladder and EEPROM correction memory. A static EEPROM memory array optimizes the power dissipation, conversion rate, inter-stage gain errors, and charge injection. The resulting converter achieves high speed operation with minimal power dissipation     

An EEPROM for microprocessors and custom logic

An EEPROM extension to a 2.5-/spl mu/ n-well CMOS technology has been developed. In this technology an EEPROM has been designed that is suitable for integration with (existing) microprocessors in a baseline 5 V technology. A 2K EEPROM memory module, usable as a building block in a cell library for custom logic, measures 3.2 mm/SUP 2/ with a memory cell area of 440 /spl mu/m/SUP 2/.     

A 4 Mb NAND EEPROM with tight programmed Vtdistribution

Described is a 5-V-only 4-Mb (512K×8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V_t) distribution, controlled by a novel program-verify technique. A tight programmed V_t distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm×15.31 mm is achieved using 1.0 μm design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance     

A high-performance very low-voltage current sense amplifier for nonvolatile memories

A high-performance sense amplifier for nonvolatile memories capable of working under a very low-voltage power supply is presented. The topology of the sense amplifier uses a pure current-mode comparison allowing power supplies lower than 1 V to be used and includes two subcircuits which improve slew rate performance. The sense amplifier was implemented in an EEPROM realized with a 0.18-/spl mu/m EEPROM technology. Experimental results showed a read access time of about 30 ns with a power supply of 1.65 V.     

一种用于温补晶振的EEPROM修调电路设计

设计了一种用于温度补偿晶体振荡器(TCXO)的数字修调电可擦除只读存储器(EEPROM)电路.该电路具有正常工作模式和RAM WRITE、EEPROM WRITE、EEPROM READ三种测试模式,用于TCXO中模拟补偿电压的修调.在SMIC 0.35μm工艺下,采用HSPICE工具对设计的电路进行了仿真与验证,结果表明该电路具有可靠性高和功耗低的优点.