一种宽电源电压带隙基准源的设计

提出一种可在宽电源电压范围下工作的带隙基准源设计.由于采用了一些新的结构,使得其电源抑制比和温度稳定性有明显提高.为支持电源管理芯片的休眠工作模式以降低待机功耗,电路中专门设置了一个辅助的微功耗基准,在正常模式下为电路提供偏置,在休眠模式中替代主基准以节省功耗.仿真结果表明,该基准源提供的1.27V基准电压在-20至120℃范围内的最大温漂为3.5mV.当供电电压由3V变化至40V时,基准电压的变化为56μV.在低于10kHz的频率范围内基准源具有大于100dB的电源抑制比.芯片采用1.5μm BCD(Bipolar-CMOS-DMOS)工艺设计与实现.实验结果证实上述设计目标已基本实现.     

一种无电阻高电源抑制比的CMOS带隙基准源

提出一种输出低于1V的、无电阻高电源抑制比的CMOS带隙基准源(BGR).该电路适用于片上电源转换器.用HJTC0.18μm CMOS工艺设计并流片实现了该带隙基准源,芯片面积(不包括pad和静电保护电路)为0.031mm2.测试结果表明,采用前调制器结构,带隙基准源电路的输出在100Hz与lkHz处分别获得了-70与-62dB的高电源抑制比.电路输出一个0.5582V的稳定参考电压,当温度在0～85℃范围内变化时,输出电压的变化仅为1.5mV.电源电压VDD在2.4～4V范围内变化时,带隙基准输出电压的变化不超过2mV.     

一种无电阻高电源抑制比的CMOS带隙基准源

提出一种输出低于1V的、无电阻高电源抑制比的CMOS带隙基准源(BGR).该电路适用于片上电源转换器.用HJTC0.18μm CMOS工艺设计并流片实现了该带隙基准源,芯片面积(不包括pad和静电保护电路)为0.031mm2.测试结果表明,采用前调制器结构,带隙基准源电路的输出在100Hz与lkHz处分别获得了-70与-62dB的高电源抑制比.电路输出一个0.5582V的稳定参考电压,当温度在0～85℃范围内变化时,输出电压的变化仅为1.5mV.电源电压VDD在2.4～4V范围内变化时,带隙基准输出电压的变化不超过2mV.     

一种带有失调消除电路的带隙基准设计

设计一种带有消除失调电压的带隙基准源。采用NEC的0.35μm 2P2M标准CMOS工艺,在Cadence Spectre环境下进行设计和仿真。该电路比传统的带隙基准电路具有更高的精度和稳定性。带隙基准的输出电压为1.274 V,在3~6 V的电源电压范围内基准电压随输入电压的最大偏移为0.4 m V;在-55~125℃的温度范围内,基准电压随温度的变化为4 m V,产生的偏置电流基本上不受电源电压的影响,而与温度成线性关系。该电路以增加芯片功耗和面积为代价,消除失调电压对电路的影响。基准电压电源抑制比可达到85 d B。     

一种超低功耗的全CMOS基准电压源设计

基于SMIC 0.13μm CMOS工艺,设计一款纳瓦级功耗的全CMOS带隙基准电路。该电路由全CMOS电路实现,避免使用三极管和电阻,实现了节省芯片面积的目的。晶体管工作在三极管区和亚阈值区,大幅降低了功耗。Cadence仿真结果表明:在-20～100℃范围内,温度系数为31 ppm/℃;在电源电压1.2～3.3 V的变化范围内,电源电压漂移系数为0.42%/V。参考电源电压下,电路的电源抑制比(PSRR)达到51.7 dB@100 Hz;室温下,电路总静态电流为22.8 nA,功耗为27.4 nW@1.2 V;该电路可调节性强,适用于低功耗芯片中。     

高精度带隙基准电压源的实现

提出了一种高精度带隙基准电压源电路,通过补偿其输出电压所经过的三极管的基极电流获得精确的镜像电流源.设计得到了在-20～+80℃温度范围内温度系数为3×10-6/℃和-85dB的电源电压抑制比的带隙基准电压源电路.该电路采用台积电(TSMC) 0.35μm、3.3V/5V、5V电源电压、2层多晶硅 4层金属(2P4M)、CMOS工艺生产制造,芯片中基准电压源电路面积大小为0.654mm×0.340mm,功耗为5.2mW.     

一种应用于TCXO的带隙基准源设计

采用CSMC 0.35μm混合工艺设计了一种应用于温度补偿晶体振荡器(TCXO)的低功耗带隙基准电压源和电压转换电路.可提供可调的多种参考电压,同时设计了启动与逻辑控制电路,确保基准电路能正常工作并降低功耗.Cadence Spectre仿真结果显示,采用3 V的电源电压,在-40℃～85℃范围内温度系数为14.5 ppm/℃,电源电压大干2.2 V即可正常启动,在正常工作情况下,基准功耗小于10μW,低频电源抑制比为83.2 dB.     

低功耗CMOS带隙基准电压源设计

从带隙基准原理出发,通过对传统的带隙基准电路中的反馈环路进行了改进,设计了一种带启动电路的带隙基准电压源。带隙基准电压源电路具有结构简单、功耗低、电压抑制比高以及温度系数低等特点。采用TSMC 0.13μm工艺对电路进行流片,管芯面积为100μm×94μm。测试结果显示,电源电压1V时,在-30~120℃范围内温度系数为6.6×10-6/℃,功耗仅1.8μW;电源电压从0.76V变化到2V,输出电压偏差仅1.52mV,电源抑制比达58dB。     

一种用于CMOS A/D转换器的带隙基准电压源

设计了一种用于CMoS A/D转换器的带隙基准电压源.该电路消除了传统带隙基准电压源中运算放大器的失调电压及电源电压抑制比对基准源指标的限制,具有很高的精度和较好的电源电压抑制比.电路采用中芯国际(SMIC)0.35μm CMOS N阱工艺.HSPICE仿真结果表明,在3.3 V条件下,在-40℃～125℃范围内,带隙基准电压源的温度系数为2.4×10-6V/℃,电源电压抑制比为88 dB@1 kHz,功耗为0.12 mW.     

一种新型的CMOS亚阈值低功耗基准电压源

利用工作于亚阈值的NMOS器件,产生两个负温度系数的电压源,然后将两个电压源作差,产生稳定的基准电压输出.整体电路采用HJTCl80 nrn标准CM（）S工艺实现.仿真结果表明,基准源输出电压为220 mV,在一25℃到100℃的温度范围内的温度系数为68×10^-6/ C.电路的最小供电电压可低至O.7 V,在供电电压O.7～4V范围内的线性调整率为1.5 mV/V.无滤波电容时,1 kHz的电源抑制比为-56 dB室温下,1.O V电压供电时,电路总体功耗为3.7μW.版图设计后的芯片核心面积为O.02 mm².本文设计的电压源适用于低电压低功耗的条件.     

A 0.19 ppm/°C bandgap reference circuit with high-PSRR

A high-order curvature-compensated CMOS bandgap reference (BGR) topology with a low temperature coefficient (TC) over a wide temperature range and a high power supply reject ratio (PSRR) is presented. High-order correction is realized by incorporating a nonlinear current I_NL, which is generated by ∆V_GS across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of 0.19 ppm/°C over the temperature range of 165 °C (−40 to 125 °C), PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.     

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8  nW at 0.6 V supply. The active area is 0.019 mm².     

A programmable voltage reference optimized for power management applications

A 3-bits programmable, low drift, high PSRR and high precision voltage reference, optimized for Power Management (PM) applications, is presented. The topology is based on a high-performance bandgap voltage reference that presents a PSRR of up to 80 dB, which is required in PM applications, because they employ mixed-signal circuits, where high frequency switching noise is present. The proposed approach was successfully verified in a standard 0.35 μm CMOS process. The experimental results confirmed that, for power supply between 3.0 and 3.3 V, and temperatures in ?20°C to 80°C range, the programmable output voltage V _REF exhibits a worst case precision of ±3%.     

一种高电源抑制比带隙基准电压源的设计

设计了一种基于反馈电路的基准电压电路。通过正、负两路反馈使输出基准电压获得了高交流电源抑制比(PSRR),为后续电路提供了稳定的电压。采用NPN型三极管,有效消除了运放失调电压对带隙基准电压精度产生的影响,并对电路进行温度补偿,大大减小了温漂。整个电路采用0.35μm CMOS工艺实现,通过spectre仿真软件在室温27℃、工作电压为4 V的条件下进行仿真,带隙基准的输出电压为1.28 V,静态电流为2μA,在-20~80℃范围内其温度系数约为18.9×10-6/℃,交流PSRR约为-107 dB。     

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I-V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient of 2.5×10⁻⁴ μA/°C in the temperature range of −40 to 150 °C at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126 dB at dc frequency and remains −92 dB at the frequency higher 1 MHz. The proposed circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.     

一种高精度BiCMOS电流模带隙基准源

采用Xfab0.35μmBiCMOS工艺设计了一种高电源抑制比（PSRR）、低温漂、输出0.5V的带隙基准源电路。该设计中,电路采用新型电流模带隙基准,解决了传统电流模带隙基准的第三简并态的问题,且实现了较低的基准电压;增加了修调电路,实现了基准电压的微调。利用Cadence软件对其进行仿真验证,其结果显示,当温度在-40～＋120℃范围内变化时,输出基准电压的温度系数为15ppm/℃;电源电压在2～4V范围内变化时,基准电压摆动小于0.06mV;低频下具有-102.6dB的PSRR,40kHz前电源抑制比仍小于-100dB。     

低温漂高PSRR新型带隙基准电压源的研制

利用带隙电压基准的基本原理,结合自偏置共源共栅电流镜以及适当的启动电路,设计了一种新型基准电压源。获得了一个低温度系数、高电源抑制比的电压基准。通过对输出端添加运算放大器,把带隙基准电路产生的1.2 V电压提高到3.5 V,提高了芯片性能。用Cadence软件和CSMC的0.5μm CMOS工艺进行了仿真,结果表明,当温度在-20～+120℃,温度系数为9.3×10-6/℃,直流时的电源抑制比为-82 dB。该基准电压源能够满足开关电源管理芯片的使用要求,并取得了较好的效果。     

一种超低功耗基准电压源设计

设计了一种用于超低功耗线性稳压器电路的基准电压源,研究了NMOSFET阈值电压的温度特性。采用耗尽/增强型电压基准结构,显著降低了功耗。采用共源共栅型结构,提高了电源抑制比。设计了数模混合集成熔丝修调网络,优化了输出电压精度和温漂。电路基于0.35μm CMOS工艺实现。仿真结果表明,在2.2~5.5 V输入电压下,基准电压为814 mV,精度可达±1%。在-40℃~125℃范围内,温漂系数为2.52×10-5/℃。低频下,电源抑制比为-99.17 dB,静态电流低至27.4 nA。