考虑量子效应的超薄体双栅肖特基源漏MOSFET电流解析模型

推导了超薄体双栅肖特基势垒MOSFET器件的漏电流模型,模型中考虑了势垒高度变化和载流子束缚效应.利用三角势垒近似求解薛定谔方程,得到的载流子密度和空间电荷密度一起用来得到量子束缚效应.由于量子束缚效应的存在,第一个子带高于导带底,这等效于禁带变宽.因此源漏端的势垒高度提高,载流子密度降低,漏电流降低.以前的模型仅考虑由于镜像力导致的肖特基势垒降低,因而不能准确表示漏电流.包含量子束缚效应的漏电流模型克服了这些缺陷.结果表明,较小的非负肖特基势垒,甚至零势垒高度,也存在隧穿电流.二维器件模拟器Silvaco得到的结果和模型结果吻合得很好.     

6H-SiC肖特基源漏n沟MOSFET的数值-解析模型

分析了6H-SiC肖特基源漏MOSFET的电流输运机制,并建立了数值-解析模型.模型正确地计入了隧道电流和势垒降低的影响,能准确反映器件的特性.模拟结果显示,源极肖特基的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好.     

6H-SiC肖特基源漏n沟MOSFET的数值-解析模型

分析了6H-SiC肖特基源漏MOSFET的电流输运机制,并建立了数值-解析模型.模型正确地计入了隧道电流和势垒降低的影响,能准确反映器件的特性.模拟结果显示,源极肖特基的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好.     

6H-SiC肖特基源漏n沟MOSFET的数值-解析模型

分析了6 H- Si C肖特基源漏MOSFET的电流输运机制,并建立了数值-解析模型.模型正确地计入了隧道电流和势垒降低的影响,能准确反映器件的特性.模拟结果显示,源极肖特基的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好.     

半导体技术

TN301 99030424热载流子简并效应研究/孔军,杨之廉(清华大学)11半导体学报.一1 998,19(11)一846一850通过把能量输运模型扩展到Fermi统计情形,用数值方法研究了简并效应对半导体器件的热载流子输运的影响,对窄基区B JT的模拟表明,当注入浓度很高时,载流子简并效应对热载流子输运的影响是不可忽略的.图3,参7(木)学报一1998,19(11)一861一864用低能量氢离子束轰击肖特基势垒二极管芯片背面,能有效减小反向电流和理想因子,增高势垒高度和减小势垒电容.对于较大的轰击能量和束流密度,特性改善的效果较显著.但过长的轰击时间会使改善的程度减…     

Ni，Ti/4H-SiC肖特基势垒二极管

采用本实验室生长的4H-SiC外延片,分别用高真空电子束蒸Ni和Ti做肖特基接触金属,Ni合金作欧姆接触,SiO_2绝缘环隔离减小高压电场集边效应等技术,制作出4H-SiC肖特基势垒二极管(SBD)。该器件在室温下反向击穿电压大于600 V,对应的漏电流为2.00×10~(-6)A。对实验结果分析显示,采用Ni和Ti作肖特基势垒的器件的理想因子分别为1.18和1.52,肖特基势垒高度为1.54 eV和1.00 eV。实验表明,该器件具有较好的正向整流特性。     

金属/有机高分子膜/n-InP肖特基势垒

本文介绍用有机高分子膜(LB膜和聚酰亚胺)代替n型InP肖特基势垒二极管中的薄氧化层,所得到的肖特基势垒二极管的势垒高度大于0.7eV,反向漏电流小于2.3×10~(-5)A/cm~2,性能稳定.还叙述了有机高分子膜的制备方法,电学测量结果,并与金属/薄氧化膜/n-InP肖特基势垒进行了比较,同时讨论了该法的优缺点.     

深亚微米FD-SOI器件亚阈模型

通过对全耗尽SOI器件硅膜中的纵向电位分布采用准三阶近似,求解亚阈区的二维泊松方程,得到全耗尽器件的表面势公式;通过引入新的参数,对公式进行修正,建立深亚微米全耗尽器件的表面势模型,能够很好地描述漏感应势垒降低效应.在此基础上,建立了亚阈漏电流模型,它能够很好的描述亚阈区的完整漏电流特性,模型计算结果与二维器件模拟软件MEDICI的模拟结果相符.     

深亚微米FD-SOI器件亚阈模型

通过对全耗尽 SOI器件硅膜中的纵向电位分布采用准三阶近似 ,求解亚阈区的二维泊松方程 ,得到全耗尽器件的表面势公式 ;通过引入新的参数 ,对公式进行修正 ,建立深亚微米全耗尽器件的表面势模型 ,能够很好地描述漏感应势垒降低效应 .在此基础上 ,建立了亚阈漏电流模型 ,它能够很好的描述亚阈区的完整漏电流特性 ,模型计算结果与二维器件模拟软件 MEDICI的模拟结果相符     

杂质分凝技术对肖特基势垒高度的调制

为降低金属或金属硅化物源漏与沟道的肖特基势垒高度以改善肖特基势垒源漏场效应晶体管(SBSD-MOSFET)的开关电流比(Ion/Ioff),采用硅化诱发杂质分凝技术(SIDS)调节NiSi/n-Si肖特基二极管(NiSi/n-Si SJD)的肖特基势垒高度,系统地研究了SIDS工艺条件如杂质注入剂量、注入能量和硅化物形成工艺对肖特基势垒高度调节的影响。实验结果表明,适当增加BF2杂质的注入剂量或能量均能显著提高有效电子势垒高度(φBn,eff),也即降低了有效空穴势垒高度(φBp,eff),从而减小反向偏置漏电流。同时,与传统的一步退火工艺相比,采用两步退火工艺形成NiSi也有利于提高有效电子势垒高度,减小反向漏电流。最后,提出了一种优化的调制肖特基势垒高度的SIDS工艺条件。     

High-Quality Schottky Contacts for Limiting Leakage Currents in Ge-Based Schottky Barrier MOSFETs

Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source–drain leakage. Here, we show that electrodeposited Ni–Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed rectification of up to five orders of magnitude. At low forward biases, the overlap of the forward current density curves for the as-deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge bandgap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four-point probe measurements indicating the lower specific resistance of NiGe as compared to Ni, which is crucial for high drive current in SB p-MOSFETs. We show by numerical simulation that by incorporating such high-quality Schottky diodes in the source/drain of a Ge channel PMOS, a highly doped substrate could be used to minimize the source-to-drain subthreshold leakage current.      

Platinum Germanosilicide as Source/Drain Contacts in P-Channel Fin Field-Effect Transistors (FinFETs)

In this paper, platinum germanosilicide (PtSiGe) was investigated extensively as an alternative to nickel germanosilicide (NiSiGe) for contact formation on silicon-germanium (SiGe) source/drain (S/D) stressors. We show that PtSiGe has superior thermal and morphological stability as compared to NiSiGe. Our results further show that the formation of PtSiGe yields a low hole barrier height (Phi_B ^P) of 215 meV in a self-aligned process. We also demonstrated the integration of PtSiGe contacts in FinFET devices. FinFETs with PtSiGe contacts achieve a 27% reduction in external resistance (R_EXT) compared to FinFETs with NiSiGe contacts. Statistical comparison reveals that the drive current performance is enhanced by 21% while maintaining comparable control of short-channel effects. These results illustrate the potential of forming contacts with low Schottky barrier heights using PtSiGe in strained transistors with SiGe S/D stressors, thereby reducing R_EXT and extending transistor performance.     

Drain conductance of junction gate FET's in the hot electron range

A new model is proposed for the drain conductance of J-FET's in the hot electron range. The model is based on a physical picture revealed through two-dimensional numerical analysis. The two-dimensional analysis shows that the electron concentration changes gradually at the boundary of a depleted region which is defined by a conventional theory. Because of this gradual change, electrons can remain after the pinch-off and contribute to the drain current. Although the high electric field causes the electron velocity to saturate, the drift velocity vector rotates into the x axis (source-to-drain) with the increase in the drain voltage. The increase in the x component Vxof the drift velocity gives rise to a small increase in drain current, that is, a finite drain conductance. The proposed model takes into account the above two essential features, gradual change in electron distribution, and the rotation of the velocity vector. This model is constructed in a single formulation which describes the current-voltage characteristics from the linear to the saturated drain-current region. Theoretical calculations agree quite well with the experiment on GaAs Schottky barrier gate FET's.     

GaSb Schottky diodes for infrared detectors

GaSb Schottky barrier photodiodes are shown to have quantum efficiency higher than 35 percent over a broad band of infra-red light wavelength shorter than 1.6 µm. Theoretical calculations of current voltage characteristics including tunneling current are compared with the experiment and it is suggested that surface leakage current, tunneling current, and avalanche breakdown, respectively, dominate the reverse characteristics with increasing voltage. Epitaxial growth of an n-type layer with carrier density 10¹⁵cm^-3and suitable surface passivation are key technologies for the application of this material to infra-red detectors.     

Selenium Segregation for Lowering the Contact Resistance in Ultrathin-Body MOSFETs With Fully Metallized Source/Drain

We report the first integration of selenium (Se) segregation contact technology in ultrathin-body (UTB) n-MOSFET featuring Ni fully silicided source and drain. During the Ni silicidation process, the implanted Se segregated at the NiSi-n-Si interface, leading to significant reduction of Schottky barrier height and contact resistance. The UTB n-MOSFETs integrated with Se segregation (SeS) contact technology show significant external series resistance reduction and drive current performance enhancement. Drain-induced barrier lowering and gate leakage current density are not adversely affected by the SeS process.     

Enhanced Gate Swing in InP HEMTs With High Threshold Voltage by Means of InAlAsSb Barrier

We demonstrated the suitability of the InP HEMTs with the InAlAsSb Schottky barrier to realize the high threshold voltage (enhancement mode), low gate current, and low power consumption. This quaternary compound material increases the conduction band discontinuity to the InGaAs channel by introducing only 10% of antimony to InAlAs. The gate current is reduced by an order of the magnitude (or even more) at gate voltage range from 0.4 to 0.8 V. On the other hand, the large conduction band discontinuity causes larger parasitic source and drain resistance, which decreases the extrinsic transconductance. Nevertheless, the high-frequency performance is comparable to the device with the conventional InAlAs barrier layer. Therefore, the InAlAsSb barrier is a promising option for logic applications, which requires reduced gate current. FETs, gate current, high-electron mobility transistors (HEMTs), high frequency.     

High-quality NiGe/Ge diodes for Schottky barrier MOSFETs

Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source–drain leakage. Here, we show that electrodeposited Ni–Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB-MOSFETs. The Schottky diodes showed rectification of up to five orders in magnitude. At low forward biases, the overlap of the forward current density curves for the as-deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge bandgap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four-point probe measurements indicating the lower specific resistance of NiGe as compared with Ni, which is crucial for high drive current in SB-MOSFETs. We show by numerical simulation that by incorporating such high-quality Schottky diodes in the source/drain of a Ge channel PMOS, highly doped substrate could be used to minimize the subthreshold source to drain leakage current.     

Hybrid Schottky injection MOS-gated power transistor

A modified Schottky injection field effect transistor (SINFET) which offers lower on-resistance and a switching speed comparable to conventional n-channel LDMOSTs is described. The fabrication process is similar to that of an LDMOS transistor but with the high-low (n+n-) `ohmic? contact at the drain replaced by a parallel combination of a Schottky barrier and a pn junction diode. This hybrid anode injects minority carriers into the n- drift region, which in turn provides conductivity modulation. A current handling capability 3.5 times larger than that of the LDMOST is achieved. With the minority carrier injection level limited by the Schottky barrier, the total amount of minority carriers injected by the hybrid anode is much lower than that injected by the pn junction diode alone. Thus, the device speed is comparable to the conventional n-channel LDMOST. By minimising the shunting resistance in the p-channel region, devices with a latch-up current density of 400 A/cm2 are obtained.     

Inhomogeneous Ni/Ge Schottky barriers due to variation in Fermi-level pinning

To achieve high performance Ge nMOSFETs it is necessary to reduce the metal/semiconductor Schottky barrier heights at the source and drain. Ni/Ge and NiGe/Ge Schottky barriers are fabricated by electrodeposition using n-type Ge substrates. Current (I)–voltage (V) and capacitance (C)–voltage (V) and low temperature I–V measurements are presented. A high-quality Schottky barrier with extremely low reverse leakage current is revealed. The results are shown to fit an inhomogeneous barrier model for thermionic emission over a Schottky barrier. A mean value of 0.57 eV and a standard deviation of 52 meV is obtained for the Schottky barrier height at room temperature. A likely explanation for the distribution of the Schottky barrier height is the spatial variation of the metal induced gap states at the Ge surface due to a variation in interfacial oxide thickness, which de-pins the Fermi level.