太赫兹Si/SiGe量子级联激光器波导模拟

波导层结构设计是制备太赫兹(THz)量子级联激光器的关键问题之一.本文基于德鲁得(Drude)模型,利用时域有限差分(FDTD)法,对Si/SiGe量子级联激光器的波导层进行优化设计,从理论上对传统的递变折射率波导、单面金属波导、双面金属波导以及金属/金属硅化物波导横磁模(TM模)的模式损耗和光场限制因子进行了对比分析.结果表明,金属/金属硅化物波导不但可以减小波导损耗,而且有很高的光学限制因子,同时其工艺也比双面金属波导容易实现,为Si/SiGe太赫兹量子级联激光器波导层的设计提供了一定的理论指导.     

太赫兹Si/SiGe量子级联激光器的能带设计

使用nextnano3模拟软件计算Si/Si1-xGex/Si量子阱的能带结构,对Si/SiGe量子级联激光器有源区的能带结构进行设计,结果表明使用Ge组分为0.27～0.3,量子阱宽度为3nm的SiGe合金与垒宽为3nm的Si层构成对称应变级联异质结构,有利于优化THz Si/SiGe量子级联激光器结构.     

太赫兹Si/SiGe量子级联激光器的能带设计

使用nextnano3模拟软件计算Si/Si1-xGex/Si量子阱的能带结构,对Si/SiGe量子级联激光器有源区的能带结构进行设计,结果表明使用Ge组分为0.27～0.3,量子阱宽度为3nm的SiGe合金与垒宽为3nm的Si层构成对称应变级联异质结构,有利于优化THz Si/SiGe量子级联激光器结构.     

太赫兹量子级联激光器

太赫兹技术近年来发展迅速,应用越来越广泛,是当前的热门研究领域。太赫兹量子级联激光器是产生太赫兹辐射的重要器件,对太赫兹量子级联激光器的发展,以及有源区和波导层的设计等进行了详细讨论。     

THz QCL波导结构研究与光束质量分析

THz量子级联激光器是理想的固态THz源,研究波导结构对激射光特性和远场光束质量的影响,是THz QCL设计中的关键。本文采用有限元方法对THz QCL双面和单面金属波导结构的限制和损耗特性进行分析,给出了限制因子、波导损耗和阈值增益随波导结构、激射波长等参数的变化关系。仿真实验结果表明:与单面金属波导相比,双面金属波导对光具有更好的限制作用,损耗也比较小,更适合做有源区的波导限制结构。在计算出波导中光场分布的基础上,又利用矢量衍射理论分析了THz QCL的光束质量,给出了不同波导宽度时出射光束的远场光束宽度和远场发散角,从应用方面为QCL的设计提供了一定参考。     

9.0μm GaAs基量子级联激光器的波导优化

通过转移矩阵法和有效折射率法计算了9.0μm GaAs基量子级联激光器波导的模式损耗和限制因子,从而对其波导结构进行优化.计算中考虑了各外延层的厚度、脊宽和腔长的影响.给出了在较低阈值下节约材料生长时间的各外延层厚度.     

单模太赫兹量子级联激光器

为了获得窄线宽太赫兹光源,制作了基于表面金属光栅的单模太赫兹量子级联激光器。通过优化光栅结构,获得了具有较强耦合效率和较低损耗的光栅结构参数。波导结构采用半绝缘表面等离子体波导以便能获得较高的光输出功率。激光器单模激射波长为95μm。10 K时,器件最高单模输出功率达到了43 m W,单模抑制比为18 d B。单模器件工作温度超过70 K,在70 K时,仍然有5 m W的单模输出功率。这种输出性能良好的激光器有望作为太赫兹接收机的本振源。     

低阈值连续波工作的2.9 THz量子级联激光器

为了获得低阈值连续波工作太赫兹源,采用固源分子束外延技术生长了GaAs/AlGaAs束缚态向连续态跃迁的太赫兹量子级联激光器(QCL)有源区,基于半绝缘-等离子体波导工艺制作了太赫兹量子级联激光器。获得了激光器(腔面未镀高反射膜)的发射光谱和相应的输出特性等性能,其中器件在10 K工作温度、350 mA激励电流下的中心频率为2.93 THz,连续波工作模式的阈值电流密度为156 A/cm2,器件的最大光输出功率为7.84 mW,最高工作温度为62 K。     

高输出功率锥形波导太赫兹量子级联激光器

制作了基于锥形波导结构的高输出功率的太赫兹(THz)量子级联激光器。激光器采用单面金属波导结构,并采用锥形波导形状提高光输出功率,且保证了良好的光斑远场发散角。激光器水平方向远场光斑发散角为18.4?,器件输出中心波长为93 μm(3.23 THz),器件最高输出功率达到了185 mW,最高工作温度为95 K。80 K时,器件的最高脉冲输出功率能达到65 mW。基于如此高的输出功率,制作了液氮杜瓦封装的小型便携式太赫兹激光源。     

9.0μm GaAs基量子级联激光器的波导优化

通过转移矩阵法和有效折射率法计算了9．0μm GaAs基量子级联激光器波导的模式损耗和限制因子，从而对其波导结构进行优化．计算中考虑了各外延层的厚度、脊宽和腔长的影响．给出了在较低阈值下节约材料生长时间的各外延层厚度．     

单晶硅化物及其应用

本文评述了单晶CoSi_2和NiSi_2的结构特点、各种制备方法、器件应用和发展前景。采用分子束外延(MBE)和“内延”法(Mesotaxy)制备的单晶硅化物质量,电学性能和热稳定性较好。由于首次得到理想的突变的金属——半导体接触,使对金属——半导体接触的理论分析成为可能。硅/单晶硅化物/硅结构在实际应用中非常重要,如单晶硅化物作集电极埋层,能降低集电极串联电阻,克服重掺杂埋层的横扩和自掺杂问题,提高了电路工作速度,减小了器件面积。埋层硅化物也可作为微波传输线的地线,是实现高频集成电路互连的好方法。而采用该结构制备的高速器件——金属基区晶体管(MBT)和穿透基区晶体管(PBT),具有很好的应用前景。     

VLSI中钛硅化物肖特基接触特性与退火条件

基于 Ti Si2 低电阻率的优点 ,采用 Ti制作肖特基二极管。在 VL SI工艺中实现同时完成钛硅化物欧姆接触和肖特基势垒二极管 (SBD)的制作。文中用 AES等技术研究不同退火工艺形成的 Ti/ Si界面形态和结构 ,寻找完善的工艺设计和退火条件。此外还测量 Al/ Ti N/ Ti/ Si结构的金属硅化物 SBD的有关特性。通过工艺实验确定 VL SI中的钛硅化物最佳的制作工艺条件     

Low-Resistance Carbon Nanotube Contact Plug to Silicon

We demonstrated the integration of carbon nanotubes (CNTs) as the contact plug to the Si MOSFET. A Ti silicide contact layer was introduced between the CNTs and the Si. The open-ended CNT tip connected the metal one on the other end. We study the contact resistivity of the CNT contact plug using the cross-bridge Kelvin test structure, and compare with the W contact plug. The CNT contact plug also showed excellent thermal stability. The electrical and thermal behavior is closely related to the intermediate layer between the CNT and the Si.      

激光熔覆MoSi2金属硅化物复合材料涂层显微组织

MoSi_2以其高熔点(2030℃)、高使用温度(>1600℃)、良好的导热性和导电性等优良性能,被认为是继镍基高温合金之后极具竞争力的新型高温结构候选材料之一。但是,MoSi_2的低温脆性和中温氧化碎裂(PEST)难以克服。本文以Mo、Si合金粉末为原料,采用激光熔覆技术,在纯镍基材上制成MoSi_2金属硅化物复合材料涂层。分析了涂层的显微组织,测试了涂层的显微硬度。     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

In-situ study of stress evolution during solid state reaction of Pd with Si(001) using synchrotron radiation

Using X-ray diffraction experiments and curvature measurements, in-situ real-time measurements of stress are performed during solid state reaction of a palladium thin film with Si(001). From X-ray diffraction measurements and using the sin²ψ method, we found out that the stress in the metal and in the silicide is compressive. This stress decreases all along the solid-state reaction for the silicide. We then compared our results with the qualitative model proposed by Zhang and d’Heurle. This model suggests the development of a high compressive stress (−2.4 GPa) in the silicide.     

Electrical characteristics of nickel silicide–silicon heterojunction in suspended silicon nanowires

Electronic characteristics of silicide/silicon interface were studied in the suspended, chemically synthesized silicon nanowires (SiNWs). Step-by-step intrusion of a silicide/Si interface along the axial direction of a suspended silicon nanowire was performed by repeated thermal annealing cycles, and the current-voltage (I-V) characteristics of the annealed silicide/SiNW/silicide structure were measured at each cycle. The intruded length of the silicide was found to be directly proportional to the total annealing time, but the rate of silicidation was much smaller than previous works on similar silicide/SiNWs. A structural kink with Ni atoms diffused along the sidewall created a secondary source of silicidation, resulting in anomalous I-V characteristics. The measured I-V including this unintentional silicidation in the Si channel was explained by various combinations of Schottky barriers and resistors.     

硅化钨MIP电容侧墙淀积工艺优化

硅化钨MIP工艺在集成电路和半导体器件制造中有着广泛的应用,但硅化钨膜在后续的侧墙工艺中容易出现剥落问题现象。通过对硅化钨材料特性,以及与电路制造相关联工艺的深入分析,发现在一定温度下,硅化钨的表面会产生富钨硅化物,它与氧气反应时会形成氧化钨,从而造成硅化钨膜的剥落。为避免氧化钨的形成,从减少富钨硅化物的形成、降低钨化硅与氧气的反应温度,以及减少参与反应的氧气量三个方面着手,在大量工艺试验的基础上提出了一种能有效防止硅化钨膜剥落的优化工艺。     

Silicidation of Ni(Yb) Film on Si(001)

The influence of the addition of Yb to Ni on the silicidation of Ni was investigated. The Ni(Yb) film was deposited on a Si(001) substrate by co-sputtering, and silicidation was performed by rapid thermal annealing (RTA). After silicidation, the sheet resistance of the silicide film was measured by the four-point probe method. X-ray diffraction and micro-Raman spectroscopy were employed to identify the silicide phases, and the redistribution of Yb after RTA was characterized by Rutherford backscattering spectrometry and Auger electron spectroscopy. The influence of the Yb addition on the Schottky barrier height (SBH) of the silicide/Si diode was examined by current–voltage measurements. The experimental results reveal that the addition of Yb can suppress the formation of the high-resistivity Ni₂Si phase, but the formation of low-resistivity NiSi phase is not affected. Furthermore, after silicidation, most of the Yb atoms accumulate in the surface layer and only a small number of Yb atoms pile up at the silicide/Si(001) interface. It is believed that the accumulation of a small amount of Yb at the silicide/Si(001) interface results in the SBH reduction observed in the Ni(Yb)Si/Si diode.