一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路

提出了一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路.通过引入一个使用亚阈值技术的基准源,电路实现了温度补偿,从而使得系统时钟在～40～100℃的范围内保持稳定.在模块设计中,提出了一些新的电路结构来降低系统功耗,其中包括一种零静态功耗的上电复位电路和一种新的稳压电路.该射频/模拟前端电路采用不带肖特基二极管0.18μm CMOS EEP-ROM工艺流片实现,它与数字基带、EEPROM一起实现了一个完整的标签芯片.测试结果表明,该芯片的最低电源电压要求为0.75V.在该最低电压下,射频/模拟前端电路的总电流为4.6μA.     

低压低功耗无源UHF RFID标签芯片模拟前端电路的设计

本文从设计符合EPCTM C1G2协议的超高频无源射频识别标签芯片的角度出发,对RFID标签芯片模拟前端电路进行设计.通过对各个关键电路的功耗与电源进行优化,实现了一个符合协议要求的低电压、低功耗的超高频无源RFID标签芯片的模拟前端.该UHF RFID标签模拟前端设计采用SMIC 0.18 μm EEPROM CMOS工艺库.仿真结果表明,标签芯片模拟前端的整体功耗控制在2.5 μW以下,工作电源可低至1 V,更好地满足了超高频无源射频识别标签芯片应用需求.     

一种超低功耗无源超高频射频识别标签芯片的设计与实现

本文提出了一种符合ISO18000-6B协议的无源超高频射频识别标签芯片设计。该芯片包括了射频/模拟前端,数字基带和512比特的EEPROM存储器。采用肖特基二极管来提高整流器的功率转换效率。详细阐述了基于峰值电流源的参考电压源的设计,该电路结构简单,并且可以满足低压、低功耗的设计要求。为了降低功耗,模拟模块工作在1v以下电源电压,并采用了一些低功耗的设计方法进一步降低数字基带的功耗。整个标签芯片采用TSMC 0.18um CMOS工艺实现,芯片尺寸为800*800um2。测试结果表明芯片的总功耗为7.4uW,灵敏度达-12dBm。     

一种13.56MHz无源射频识别模拟前端的设计

提出了一种基于ISO/IEC18000-3协议的高频13.56MHz射频识别(RFID)标签芯片的模拟前端电路结构,采用Chartered 0.35μm EEPROM工艺进行流片验证。该芯片实现了无源RFID标签芯片通信时所需的整流、稳压供电、时钟恢复、信号解调以及副载波调制的全部功能。     

射频识别芯片设计中时钟树功耗的优化与实现

UHF RFID是一款超高频射频识别标签芯片,该芯片采用无源供电方式,对于无源标签而言,工作距离是一个非常重要的指标,这个工作距离与芯片灵敏度有关,而灵敏度又要求功耗要低,因此低功耗设计成为RFID芯片研发过程中的主要突破点。在RFID芯片中的功耗主要有模拟射频前端电路,存储器,数字逻辑三部分,而在数字逻辑电路中时钟树上的功耗会占逻辑功耗不小的部分。本文着重从降低数字逻辑时钟树功耗方面阐述了一款基于ISO18000-6Type C协议的UHF RFID标签基带处理器的的优化和实现。     

UHF RFID标签芯片模拟射频前端设计

对射频识别标签芯片系统结构及工作原理进行分析,设计应用于符合ISO18000—6C／B两种标准的UHFRFID标签芯片的模拟射频前端,主要包括整流电路、稳压电路、调制／解调电路、上电复位及时钟产生电路。模拟射频前端芯片采用TSMC0．18μm CMOS混合信号工艺流片验证。测试结果表明,所研制的模拟射频前端性能满足UHF RFID标签芯片系统要求。     

低成本射频识别标签模拟前端分析与设计

提出一种新的低成本射频识别标签模拟前端,同时兼容ISO 14443A和ISO 14443B协议.相比于传统模拟前端,本设计采用面积更小的单线圈天线代替传统大面积多圈天线,使得标签的封装成本大幅度降低.考虑到单线圈天线的性能降低,设计了一个新的具有高效率低启动电压的电荷泵整流电路.整体电路采用SMIC 0.18μm EEPROM工艺实现,测试结果显示电荷泵驱动120kΩ等效负载时,整流效率达到36%,输入交流幅度仅0.5V时,输出电压达到电路工作电压1V.标签的阅读距离可以达到22cm.     

低成本射频识别标签模拟前端分析与设计

提出一种新的低成本射频识别标签模拟前端,同时兼容ISO 14443A和ISO 14443B协议.相比于传统模拟前端,本设计采用面积更小的单线圈天线代替传统大面积多圈天线,使得标签的封装成本大幅度降低.考虑到单线圈天线的性能降低,设计了一个新的具有高效率低启动电压的电荷泵整流电路.整体电路采用SMIC 0.18μm EEPROM工艺实现,测试结果显示电荷泵驱动120kΩ等效负载时,整流效率达到36%,输入交流幅度仅0.5V时,输出电压达到电路工作电压1V.标签的阅读距离可以达到22cm.     

2.45GHz电子射频标签模拟前端芯片的研制

分析了RFID系统的组成和基本原理,针对超高频EPC C1G2协议,提出半无源及有源电子标签前端结构及参考电路,包括整流器、偏置单元、上电复位、解调、反向散射调制、振荡器等部分.采用多种方法,极大程度上实现了电路整体的低功耗,并且采取了限幅、ESD电路,保障了电路的稳定性.采用标准CMOS工艺,设计出了低功耗、低电压工作的2.45 GHz射频模拟前端芯片电路,芯片在0.8～1.8 V电压内均可正常工作.芯片的静态工作电流为2μA,芯片工作时,平均工作电流约为65μA.     

无源UHF RFID标签芯片模拟前端电路设计探讨

本文根据协议的相关要求,设计了无源UHF RFID标签芯片模拟前端电路,并重点对标签芯片模拟前端的关键技术进行了优化,实现了标签芯片模拟前端电路。最终,电路的仿真结果表明标签芯片的模拟前端电压较为稳定,且功耗较小,稳定的时钟频率能够帮助系统进行正确的输入信号解调,实现了协议要求的电路设计。     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

一种低功耗高动态范围的915MHz无源射频标签

设计了一种适用于NCITS-256-1999协议的915MHz无源射频只读标签.芯片具有低功耗、高动态范围的特点.1.6V电源电压下模拟前端的静态工作电流为1.6μA,芯片正常工作所需要的最小射频信号输入功率为45μW.芯片在0.18μm CMOS工艺下流片验证,测试结果表明,芯片能够很好地满足设计要求.     

无源射频电子标签模拟前端的设计与分析

提出了与ISO/IEC 18000-3兼容的高频无源射频电子标签模拟前端.分析了设计中的考虑因素,尤其是射频电子标签的能量传输.基于这些分析,提出了一种新架构、高能量转换效率、低电压、低功耗、在噪声和能量波动环境下具有高性能的模拟前端.此电路在Chartered 0.35μm标准CMOS工艺下实现,测试结果表明芯片能很好地满足设计要求.     

Design of an analog front-end for ambulatory biopotential measurement systems

A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented.The front-end circuit is capable of amplifying and conditioning different biosignals.To optimize the power consumption and simplify the system architecture,the front-end only adopts two-stage amplifiers.In addition, careful design eliminates the need for chopping circuits.The input-referred noise of the system is only 1.19μVrms (0.48-2000 Hz).The chip is fabricated via a SMIC 0.18μm CMO...     

一种基于OFDM的新型低功耗RF收发器设计

为实现低功耗信号传输,提出一种基于OFDM的IEEE 802.15.4g低功耗无线电频率（RF）收发器。该新型RF收发器电路由Tx BBA（基带模拟）、片上RF开关前端、Rx BBA及锁相环（PLL）构成,采用0.18?m CMOS技术制作,满足了IEEE 802.15.4g OFDM系统低功耗信号传输的需要。实际测试结果显示,相比传统的RF收发器,提出的RF收发器具有较低的功耗和良好的灵敏度,当电源电压为1.8 V时,Tx模式下会消耗14.7mA,Rx模式下会消耗15.7mA。     

A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

正A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC(automatic gain control) and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL(sound pressure level).Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power(48μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35μm(V_(TON) + |V_(TOP)|≈1.35 V).The THD is below -45 dB.The fabricated chip only occupies the area of 1×0.5 mm~2 and 1×1 mm~2.     

应用于S波段AESA的射频收发前端设计

采用0．18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3．3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5．0dBm,射频输出在2～3．5GHz频带内电压增益为6．3～9．2dB,噪声系数小于14．5dB;接收前端工作电流为50mA,输入1dB压缩点为-5．6dBm,射频输入在2～3．5GHz频带内电压增益为12—14．5dB,噪声系数小于11dB;所有端口电压驻波比均小于1．8：芯片面积1．8×2．6mm0。     

A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends

As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However, the supply voltage and power consumption of the RF front-end and analog sections do not scale in a similar fashion. In fact, in many state-of-the-art communication transceivers, RF and analog sections can consume more energy compared to the digital part. In this paper, first, a system level energy model for all the components in the RF and analog front-end is presented. Next, the RF and analog front-end energy consumption and communication quality of three representative systems are analyzed: a single user point-to-point wireless data communication system, a multi-user code division multiple access (CDMA)-based system and a receive-only video distribution system. For the single user system, the effect of occupied signal bandwidth, peak-to-average ratio (PAR), symbol rate, constellation size, and pulse-shaping filter roll-off factor is analyzed; for the CDMA-based multi-user system, the effect of the number of users in the cell and multiple access interference (MAI) along with the PAR and filter roll-off factor is studied; for the receive-only system, the effect of 1/f noise for direct-conversion receiver and the effect of IF frequency for low-IF architecture on the RF front-end power consumption is analyzed. For a given communication quality specification, it is shown that the energy consumption of a wireless communication front-end can be scaled down by adjusting parameters such as the pulse shaping filter roll-off factor, constellation size, symbol rate, number of users in the cell, and signal center frequency     

A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system

This work presents the design and implementation of a 2.4 GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25 μm CMOS. The prototype integrates a low-IF receiver analog front-end (low noise amplifier, double-balanced down-converter, band-pass-filtered AGC loop, and ASK demodulator) and a direct-conversion transmitter analog front-end (20 MHz IF PLL with well-defined amplitude control circuit, ASK modulator, up-converter, and output buffer) on a single chip together with one integrated RF oscillator and two LO buffers. Trade-off has been made over the design boundaries of the different building blocks to optimize the overall system performance. All building blocks feature the circuit topologies that enable comfortable operation at low power consumption. As a result, the IC works at a 2.5 V power supply, while only consuming 15 mW in receiver (RX) mode and 14 mW in transmitter (TX) mode. To build a complete transceiver for the endoscopy capsule system, only an antenna, a duplexer, and a digital controller are needed besides the presented analog front-end chip.