802.11b收发系统中的全集成低功耗发送机设计

基于SMIC 0.18μm CMOS工艺,设计了一个应用于IEEE 802.11b收发系统的全集成低功耗发送机. 直接转换发送机包括两个Chebyshev I型低通滤波器,两个可编程增益放大器(PGA),一个单边带混频器和一个功率预放大器. 发送机以3dB为步长提供32dB增益,其最大输出功耗为-3.4dBm, EVM为6.8%. 工作在1.8V电源电压,发送机的功耗仅57.6mW. 发送机芯片面积为1.6mm×1.6mm.     

0.8～8.5 GHz宽带单片低噪声放大器

利用负反馈放大器设计原理,采用GaAs PHEMT工艺技术,设计制作了一种微波宽带GaAs PHEMT低噪声放大器芯片,并给出了详细测试曲线.该放大器由两级组成,采用负反馈结构,工作频率0.8～8.5 GHz,整个带内功率增益19 dB,噪声系数1.55 dB,增益平坦度小于±0.7 dB,输入驻波比1.6,输出驻波比1.8,1 dB压缩点输出功率大于10 dBm,芯片内部集成偏置电路,单电源 5 V供电,芯片具有良好的温度特性.该芯片面积为2.5 mm × 1.2 mm.     

1.6GHz高线性度低功耗CMOS驱动放大器

提出了一种高线性度低功耗驱动放大器的设计方法,这种设计方法采用最佳偏置(Optimum Biasing)的线性化技术提高线性度.利用这种方法设计了一个工作在1.6GHz的两级驱动放大器,第一级预放大器采用1.8V电源电压,第二级输出放大器采用3.3V电源电压.放大器在TSMC 0.18μM CMOS 工艺下仿真,仿真结果显示放大器的电压增益为31.8dB,三阶交调截取点(OIP3)为20.0dBm,输出1dB压缩点为17.7dBm,输出饱和功率为19.3dBm,静态功耗小于40mW.     

用于数字电视接收机中PGA的设计

本文采用新型的电流模放大器和可编程的电阻反馈网络设计了一种高线性度的可编程增益放大器(PGA),单级的电压增益范围为0～20dB,增益步长0.5dB,3dB带宽1.7MHzMHz,两个输入谐波(tone)的频率为0.2MHz和0.3MHz,输出摆幅为峰峰值1V时,IM3大于60dB.在3.3V电源电压时功耗为2.38mW.     

用于77GHz毫米波雷达的模拟基带电路设计

实现了一个带宽和增益可配置、高线性度、低噪声的模拟基带电路,可应用于77 GHzCMOS毫米波雷达接收机.电路包括一个带宽可配置的5阶巴特沃斯低通滤波器模块、三个可编程增益放大器模块以及三个直流失调消除环路.增益范围为18～70 dB,增益步进为6 dB;带宽为200 kHz～2 MHz;噪声系数最小为24 dB;输出1-dB压缩点为5.1 dBm,在最高增益时,IIP3为-52dBm;功耗为14.6 mA@1 V.电路采用65 nm CMOS工艺实现,芯片面积为1.2×0.93 (mm2).     

应用于无线传感网的低功耗PGA设计

可编程增益放大器(PGA)主要应用于无线传感网络射频前端接收机芯片.PGA的设计采用0.18 μm RF CMOS工艺,以负载可编程为基础实现增益可变.PGA电压增益范围1～60 dB,增益步长1 dB,增益误差小于0.5 dB,中心频率为2MHz,3 dB带宽大于3.2 MHz.通过控制放大器尾电流源工作与否来实现功耗管理.当电源电压为1.8 V时,最大功耗为4mw,最小功耗为1.3 mW.通过仿真验证,PGA性能能够满足系统设计要求.     

CMOS宽带可变增益放大器

设计了一种CMOS宽带、低功耗可变增益放大器.在分析使用源极退化电阻的共源放大器高频特性基础上,通过加入频率补偿电容改变放大器的零极点分布,在不增加功耗的情况下扩展了带宽.分析了放大器在低增益下出现的增益尖峰现象并加以解决.使用跨导增强电路提高了放大器的线性度.两级可变增益放大器使用TSMC0.25μm CMOS工艺.仿真结果表明,放大器在3.3V电压下核心电路功耗为3.15mW,增益范围0～40dB;在负载为5pF电容时3dB带宽大于340MHz,输出三阶交调点高于3.5dBm.     

CMOS宽带可变增益放大器

设计了一种CMOS宽带、低功耗可变增益放大器.在分析使用源极退化电阻的共源放大器高频特性基础上,通过加入频率补偿电容改变放大器的零极点分布,在不增加功耗的情况下扩展了带宽.分析了放大器在低增益下出现的增益尖峰现象并加以解决.使用跨导增强电路提高了放大器的线性度.两级可变增益放大器使用TSMC0.25μm CMOS工艺.仿真结果表明,放大器在3.3V电压下核心电路功耗为3.15mW,增益范围0～40dB;在负载为5pF电容时3dB带宽大于340MHz,输出三阶交调点高于3.5dBm.     

采用电流复用技术的8mm频段低噪声放大器

利用电流复用技术设计8mm频段低噪声放大器芯片,采用0.15μm GaAs PHEMT工艺,芯片尺寸为1.73mm×0.75mm×0.1mm。测试结果显示:在32～38GHz频带内,放大器增益大于21dB,噪声系数小于1.85dB,输入、输出电压驻波比小于2.5,P1 dB大于7dBm,功耗5V,28mA,采用电流复用技术比传统设计的功耗降低将近40%。     

多通道神经信号再生集成电路

介绍了一个六通道的神经信号再生集成电路.每一个通道均由检测电路和激励电路组成.检测电路用低噪声、高共模抑制比的仪器放大器从神经元的上端探测神经信号.激励电路中,采用反相运算放大器来进一步放大神经信号,放大的神经信号通过一个缓冲器来激励受损神经的下端神经元,实现了神经信号的传递,从而实现再生的功能.电路采用CSMC0.5 μm CMOS工艺设计,整个六通道的芯片版图面积为1.9 mm×1.6 mm.电路的后仿结果如下:在士2.5 V的供电电压下,单通道电路的功耗为3.9 mW;在100 Hz到7 kHz的频率范围内,等效输入噪声为25.4 nV/sqrt(Hz);增益带宽积达到7.6MHz,可实现60 dB到110 dB的可调增益,输出阻抗为6.2 Ω.     

A low-power 2.4-GHz transmitter/receiver CMOS IC

A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using a single 1.6-GHz local oscillator, the transceiver employs two upconversion and downconversion stages while providing on-chip image rejection filtering. Realized in a 0.25-/spl mu/m digital CMOS technology, the receiver exhibits a noise figure of 6 dB and consumes 17.5 mW from a 2.5-V supply, and the transmitter delivers an output power of 0 dBm with a power consumption of 16 mW.     

A design of a high-speed and high-efficiency capsule endoscopy system

This paper presents a high-speed and high-efficiency capsule endoscopy system. Both a transmitter and a receiver were optimized for its application through an analysis of the human body channel. ON-OFF keying modulation is utilized to achieve low power consumption of the in-body transmitter. A low drop output regulator is adopted to prevent performance degradation in the event of a voltage drop in the battery. The receiver adopts superheterodyne structure to obtain high sensitivity, considering the link budget from the previous analysis. The receiver and transmitter were fabricated using the CMOS 0.13-μm process. The output power of the transmitter is -1.6 dB·m and its efficiency is 27.7%. The minimum sensitivity of the receiver is -80 dB·m at a bit error ratio (BER) of 3 × 10 (-6). An outer wall loop antenna is adopted for the capsule system to ensure a small size. The integrated system is evaluated using a liquid human phantom and a living pig, resulting in clean captured images.     

基于GaN HEMT的13～17 GHz收发多功能芯片

基于GaN高电子迁移率晶体管(HEMT)工艺设计制作了一款收发(T/R)多功能芯片(MFC),主要用于射频前端收发系统.该芯片集成了单刀双掷(SPDT)开关用于选择接收通道或发射通道工作,芯片具有低噪声性能、高饱和输出功率和高功率附加效率等特点.芯片接收通道的LNA采用四级放大、单电源供电、电流复用结构,发射通道的功率放大器采用三级放大、末级四胞功率合成结构,选通SPDT开关采用两个并联器件完成.采用微波在片测试系统完成该芯片测试,测试结果表明,在13～ 17 GHz频段内,发射通道功率增益大于17.5 dB,输出功率大于12W,功率附加效率大于27％.接收通道小信号增益大于24 dB,噪声系数小于2.7 dB,1 dB压缩点输出功率大于9 dBm,输入/输出电压驻波比小于1.8∶1,芯片尺寸为3.70 mm×3.55 mm.     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

Integrated circuits for a 200 Mbit/s fiber-optic link

A set of three bipolar integrated circuits for a new fiber-optic link is described. The link operates at data rates of 5-200 Mb/s NRZ. The optical transmitter and receiver modules are compact and fit into standard 16-pin dual-in-line sockets. The power consumption of the transmitter module is 530 mW and the receiver module dissipates 310 mW. The optical loss budget is 20 dB, which is sufficient for link lengths of up to 5 or 6 km. The circuits have been designed in a 3-/spl mu/m bipolar process. The chip sizes are 2 mm/spl times/1.75 mm each.     

A 7-GHz-band subminiature FPU transmitter

A compact, low-cost, light-weight field pick-up (FPU) transmitter developed for emergency news gathering is described. It consists of a 7 GHz band FET direct frequency modulator and a flat-panel antenna. The modulator uses a FET, a dielectric resonator, and two varactors. The use of two varactors magnetically coupled with the dielectric resonator results in good modulation linearity and, therefore, a linearizer before the modulator is not required. The modulator has an output power of 22 dBm, differential gain of less than 3%, and differential phase of less than 2°. The antenna is constructed of four rectangular microstrip patches on a Teflon-glass substrate and has outer dimensions of 90 mm×90 mm and a gain of 13 dBi. The dimensions of the transmitter are 60 mm×45 mm×90 mm and the weight is 300 g. Using the transmitter with a 4 dB noise-figure receiver and a 60 cm diameter parabolic receiving antenna, the unweighted signal-to-noise ratio obtained for an NTSC TV signal is 42 dB after a 10 km transmission     

应用于S波段AESA的射频收发前端设计

采用0．18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3．3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5．0dBm,射频输出在2～3．5GHz频带内电压增益为6．3～9．2dB,噪声系数小于14．5dB;接收前端工作电流为50mA,输入1dB压缩点为-5．6dBm,射频输入在2～3．5GHz频带内电压增益为12—14．5dB,噪声系数小于11dB;所有端口电压驻波比均小于1．8：芯片面积1．8×2．6mm0。     

适于视频应用的高数据传输率集成CMOS收发机

这篇文章给出了一个5GHz CMOS射频收发机的设计方案。此设计采用0.18微米射频CMOS加工工艺,集合了最新IEEE802.11n的特性例如多输入多输出技术的专利协议以及其他无线技术,可提供应用在家庭环境中的实时高清电视数据的无线高速传输。设计频率涵盖了从4.9GHz到5.9GHz的ISM频带,每个射频信道的频宽为20MHz。收发机采用了直接上变频发射器和低中频接收器的结构。在没有片上校准的情况下,设计采用双正交直接上变频混频器,得到了超过35dB的镜像抑制。测试结果得到6dB接收机噪声系数以及在-3dBm输出功率时得到发射机EVM结果优于33dB。     

Optical time-division multiplexed transmission at 8 Gbit/s using single laser and semiconductor optical power amplifier

The authors report transmission over 57 km of single-mode fibre in a two-channel, 8 Gbit/s optical time-division multiplexed system experiment using a transmitter with a single laser and a semiconductor optical power amplifier at the transmitter output. The amplifier operates with a net gain of 11.5 dB, which corresponds to 0.8 dB gain compression, and a fibre coupled output power of +6 dBm. The amplifier facet output power for which the gain is compressed by 3 dB is +13 dBm. The experimental system uses neither an isolator nor an optical filter.<>     

Parallel optical interconnection for uncoded data transmission with1 Gb/s-per-channel capacity, high dynamic range, and low powerconsumption

The design, realization, and characterization of a multichannel dc-coupled ECL-voltage compatible parallel optical interconnection with a bit rate of up to 1 Gb/s-per-channel is reported. The transmitter module consists of an array of laser diodes with low threshold currents and the 50 Ω matching network, the receiver module of a photo diode array and an amplifier array. All the opto-electronic and electronic components are fabricated as arrays with a pitch of 250 μm. The total power consumption is 110 mW per channel, For a BER <10¹⁴ the dynamic range is 15 dB for a bit rate per channel of 200 Mb/s, 13 dB for 630 Mb/s, and 8 dB for 1 Gb/s. The channel crosstalk is below -48 dB (electrical). The size of the opto-electronic parts (12 channels, without electrical connectors) is only 10 mm (length)×5 mm (width)×4 mm (height)