Automata for learning sequential tasks

This paper describes a system that is capable of learning both combinational and sequential tasks. The system learns from sequences of input/output examples in which each pair of input and output represents a step in a task. The system uses finite state machines as its internal models. This paper proposes a method for inferring finite state machines from examples. New algorithms are developed for modifying the finite state machines to allow the system to adapt to changes. In addition, new algorithms are developed to allow the system to handle inconsistent information that may result from noise in the training examples. The system can handle sequential tasks involving long-term dependencies for which recurrent neural networks have been shown to be inadequate. Moreover, the learned finite state machines are easy to be implemented in VLSI. The system has a wide range of applications including but not limited to (a) sequence detection, prediction, and production, (b) intelligent macro systems that can learn rather than simply record sequences of steps performed by a computer user, and (c) design automation systems for designing finite state machines or sequential circuits. C. H. Ben CHOI, Ph.D.: He got his B. S., M. S., and Ph.D. degrees all from The Ohio State University in the United States. His major areas of study include Solid State Microelectronics, Computer Engineering, and Computer Information Science. He has works on general associative memory, parallel and distributed computer architectures, and machine learning. He currently works on a project concerning theoretical aspects of learning machine. His research interests include hardware and software methods of building an intelligent machine.     

VLSI asynchronous systems: specification and synthesis

Most of today's digital systems are realized using synchronous (i.e. globally clocked) VLSI circuits. For many reasons, it is becoming increasingly hard to build large synchronous circuits. Although several techniques for building non-clocked (i.e. asynchronous) sequential circuits have been known for some time, they have been largely ignored by the digital design community. Recently, however, asynchronous circuits have been enjoying a revival. After reviewing recent research in this area, we take a simple collection of examples and, through them, explain our design system for specifying and synthesizing asynchronous circuits. We show that by being able to work in a framework where circuit activities do not have to coincide with clock pulses, designers obtain several avenues for circuit optimization that are highly promising for creating efficient and modularly expandable circuits.     

VLSI technologies for artificial neural networks

VLSI systems, basic integrated circuits, and silicon technologies are discussed. Novel circuit and design principles that provide a foundation for the implementation of a wide variety of neural network models in silicon are described. The key issues for a successful integration of neural systems are identified. The realization of algorithms in silicon is examined. Special-purpose hardware for carrying out the activation and transfer function and for the connection elements is discussed. A brief overview of the current silicon technologies is provided     

General decomposition of incompletely specified sequential machines with multi-state behavior realization

This paper is devoted to decomposition of sequential machines, discrete functions and relations. Sequential machine decomposition consists in representation of a given machine as a network of collaborating partial machines that together realize behavior of the given machine. A good understanding of possible decomposition structures and of conditions under which the corresponding structures exist is a prerequisite for any adequate circuit or system synthesis. The paper discusses the theory of general decomposition of incompletely specified sequential machines with multi-state behavior realization. The central point of this theory is a constructive theorem on the existence of the general decomposition structures and conditions under which the corresponding structures exist. The theory of general decomposition presented in this paper is the most general known theory of the binary, multi-valued and symbolic sequential and combinational discrete network structures. The correct circuit generator defined by the general decomposition theorem covers all other known structural models of sequential and combinational circuits as its special cases. Using this theory, in recent years we developed a number of effective and efficient methods and EDA tools for sequential and combinational circuit synthesis that consistently construct much better circuits than other academic and commercial state-of-the-art synthesis tools. This demonstrates the practical soundness of our theory. This theory can be applied to any sort of binary, multi-valued and symbolic systems expressed as networks of relations, functions or sequential machines, and can be very useful in such fields as circuit and architecture synthesis of VLSI systems, knowledge engineering, machine learning, neural network training, pattern analysis, etc.     

Synaptic dynamics in analog VLSI

Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.     

大学编程语言课实例教学探讨

本文以"C++程序设计"课程为对象,探讨了大学编程语言课的实例教学方法,进行了C++程序实例设计,并提出构建一个基于Web的程序实例自学系统,弥补了课堂教学实例数量不足的问题,同时在系统中提供了自适应实例学习控制策略作为学生实例学习的指导。     

A generic systolic array building block for neural networks withon-chip learning

Neural networks require VLSI implementations for on-board systems. Size and real-time considerations show that on-chip learning is necessary for a large range of applications. A flexible digital design is preferred here to more compact analog or optical realizations. As opposed to many current implementations, the two-dimensional systolic array system presented is an attempt to define a novel computer architecture inspired by neurobiology. It is composed of generic building blocks for basic operations rather than predefined neural models. A full custom VLSI design of a first prototype has demonstrated the efficacy of this design. A complete board dedicated to Hopfield's model has been designed using these building blocks. Beyond the very specific application presented, the underlying principles can be used for designing efficient hardware for most neural network models.     

Real-time computing without stable states: a new framework for neural computation based on perturbations

A key challenge for neural modeling is to explain how a continuous stream of multimodal input from a rapidly changing environment can be processed by stereotypical recurrent circuits of integrate-and-fire neurons in real time. We propose a new computational model for real-time computing on time-varying input that provides an alternative to paradigms based on Turing machines or attractor neural networks. It does not require a task-dependent construction of neural circuits. Instead, it is based on principles of high-dimensional dynamical systems in combination with statistical learning theory and can be implemented on generic evolved or found recurrent circuitry. It is shown that the inherent transient dynamics of the high-dimensional dynamical system formed by a sufficiently large and heterogeneous neural circuit may serve as universal analog fading memory. Readout neurons can learn to extract in real time from the current state of such recurrent neural circuit information about current and past inputs that may be needed for diverse tasks. Stable internal states are not required for giving a stable output, since transient internal states can be transformed by readout neurons into stable target outputs due to the high dimensionality of the dynamical system. Our approach is based on a rigorous computational model, the liquid state machine, that, unlike Turing machines, does not require sequential transitions between well-defined discrete internal states. It is supported, as the Turing machine is, by rigorous mathematical results that predict universal computational power under idealized conditions, but for the biologically more realistic scenario of real-time processing of time-varying inputs. Our approach provides new perspectives for the interpretation of neural coding, the design of experiments and data analysis in neurophysiology, and the solution of problems in robotics and neurotechnology.     

Implementation of multilayer neural network with threshold neurons and its analysis

In this paper, the implementation of new digital architecture for a multilayer neural network (MNN) with on-chip learning is discussed. The advantage of using the digital approach is that it can use state-of-the-art VLSI and ULSI implementation techniques. One of the major hard-ware problems in implementing a neural network is the activating function of the neurons. The proposed MNN uses a simple function as the neuron's activating function to reduce the circuit size. Moreover, the proposed MNN has an on-chip learning capability. As the learning algorithm, a backpropagation algorithm is modified for effective hard-wave implementation. The proposed MNN is implemented on a field-programmable gate array (FPGA) to evaluate the learning performance and circuit size. This work was presented, in part, at the Third International Symposium on Artificial Life and Robotics, Oita, Japan, January 19–21, 1998     

Optimal floating point multiplication processor for signal processing

The design of a floating point matrix- vector multiplication processor array for VLSI, which has an optimal area-time complexity product, is presented. This processor array is capable of performing the function (where n = 1,…, N) and can be applied in many digital signal processing applications, by simply changing the matrix coefficients stored in that array. Each N-bit mantissa, M-bit exponent (N, M) processor element of the array comprises a mantissa multiplier/adder circuit and hardware to handle the floating point control. The multiplier/adder circuit is implemented by a new optimal algorithm, which is regular, recursive and fast. Secondly, the algorithm offers a highly local and regular interconnection network, which is a fundamental requirement in VLSI circuit design methodology.     

Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus

The reliability of FPGA based hardware designs has become an important field of research particularly for space computing. Traditionally, redundancy is utilized in FPGA based designs to achieve reliable or error-tolerant computing. However, the redundant designs vary according to the granularity level and the voter placement algorithms used for the hardware design. The resulting circuit configurations vary in area, latency and power as well as in the achieved reliability. While the evaluation of area, latency and power is done by the FPGA design tools, quantitative data for reliability are usually not derived. Consequently, there is a need for an automated reliability evaluation tool especially considering the huge design space of redundant circuit structures. In this paper, we combine the Boolean difference error calculator (BDEC), a probabilistic reliability model for hardware designs, with a reliability model for fault-tolerant circuit structures. As a result, we are able to study the reliability of fault-tolerant circuit structures at the logic layer. We focus on fault-tolerant circuits to be implemented in FPGAs and show how to extend our combined model from combinational to sequential circuits. For an automated analysis, we develop a MATLAB-based tool utilizing our extended BDEC model. With this tool, we conduct a case study on dynamic reliability management and show how quantitative reliability data obtained from this tool improves the four-dimensional Pareto optimization for area, latency, power and reliability.     

某型防空导弹国产化数字板测试仪设计

针对某型防空导弹数字电路板国产化工作,设计了一种用于对仿制板进行功能测试验证的数字板测试仪;测试仪设计引入虚拟仪器的概念,采用层次化、模块化和标准化的思想,硬件方面主要利用CPLD与USB技术实现了系统的通信与控制,软件方面采用Lab Windows/CVI实现了测试仪的应用程序设计;实践证明,该测试仪是一种能够最大限度利用计算机资源、支持热插拔、价格低廉的新型虚拟仪器测试仪,较好地完成了国产化板的功能验证任务.     

数字电路串扰故障测试的路径敏化方法研究

数字电路集成度的提高特别是近年来系统芯片的出现,信号线之间的间距不断缩小,使得信号线间容易发生串扰.文章首先对串扰故障模型,特别是信号线间容性和感性耦合所产生的串扰及其特征进行了讨论,其次针对数字电路中串扰故障的检测,研究了基于路径敏化的测试矢量生成方法,给出了方法的实现步骤.     

Pulse-stream VLSI neural networks mixing analog and digitaltechniques

The pulse-stream technique, which represents neural states as sequences of pulses, is reviewed. Several general issues are raised, and generic methods appraised, for pulsed encoding, arithmetic, and intercommunication schemes. Two contrasting synapse designs are presented and compared. The first is based on a fully analog computational form in which the only digital component is the signaling mechanism itself-asynchronous, pulse-rate encoded digital voltage pulses. In this circuit, multiplication occurs in the voltage/current domain. The second design uses more conventional digital memory for weight storage, with synapse circuits based on pulse stretching. Integrated circuits implementing up to 15000 analog, fully programmable synaptic connections are described. A demonstrator project is described in which a small robot localization network is implemented using asynchronous, analog, pulse-stream devices.     

基于FPGA的Kohonen竞争网络硬件实现

本文介绍了神经网络VLSI硬件实现的基本情况和VerilgHDL硬件设计方法的概念．在此基础上利用FPGA设计出了Kohonen竞争网络硬件电路。其工作频率为33Mhz．并对其工作过程进行了较详细的分析．给出了综合仿真的测试结果。     

Hierarchical timing verification system

A hierarchical timing verification system, based on critical path analysis technique, is described. These techniques permit the system to identify the critical paths of the logic designs. The system performs timing analysis on VLSI designs with sequential circuits and feedback loops. The system traces the design both in the forward and backward directions and computes the arrival times and required arrival times at the primary inputs and primary outputs of the design. The results are applicable to hierarchical VLSI design methodologies. This system has been tested using the logic of Sperry's 1100 series mainframe computer system.     

深度学习模型鲁棒性研究综述

在大数据时代下,深度学习理论和技术取得的突破性进展,为人工智能提供了数据和算法层面的强有力支撑,同时促进了深度学习的规模化和产业化发展.然而,尽管深度学习模型在现实应用中有着出色的表现,但其本身仍然面临着诸多的安全威胁.为了构建安全可靠的深度学习系统,消除深度学习模型在实际部署应用中的潜在安全风险,深度学习模型鲁棒性分...     

复杂数字电路多级在线进化技术研究

复杂数字电路的在线进化是目前演化硬件领域的难题之一.本文阐述了基于多级分解进化的复杂数字电路在线进化思想,给出了数字电路进化设计算法,分析了数字电路编码方案,研究了数字电路在线验证评估方法,设计了适应度函数,给出了数字电路在线进化设计实验系统方案.以典型数字电路为例,验证了多级分解进化方法的有效性,实验结果表明,采用多级分解进化方法可大大提高数字电路在线进化设计的速度与成功率,也有利于提高数字电路在线验证评估效率.