Decimation for Sigma Delta Modulation

Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.     

1比特Sigma Delta调制在DSD中的应用

本文结合Sigma Delta调制的原理,解释了1-bitSigma Delta调制在DSD的A/D,D/A技术中的应用,以及其噪声整形的功能。同时,在文章的结尾,结合当前SACD制作的发展方向,展望DSD设备在未来高品质录音中的前景及应用。     

Delta Sigma转换器的简化

Delta Sigma(A-∑)转换器属于所谓的降噪式(noise-shaped)过采样(oversampled)模拟-数字变换器(ADC).它们是一些高度非线性的系统,其原理对现有的完全解析处理方法提出了挑战,在线性化模型的帮助下,通过仿真也可以完整的了解其性能.     

Asymptotic Performance of Delayed Delta Coding with Single and Double Integration

A study of the asymptotic performance of delta coding with delayed decision is presented for the cases of first and second order integration assuming a stationary, bandlimited Gaussian source. The resulting signal-to-distortion-ratio serves as an upper bound for any delayed (multipath) decision scheme provided that the sampling rate exceeds the Nyquist rate by a factor greater than about two. The analysis shows that the improvement offered by delayed encoding relative to ordinary delta modulation has its basic origin in diminished overload distortion. Some insight is given into how the improvement is related to the decoding filter. Finally, numerical results are given for some sources with speech-like spectra     

ΣΔ调制器的设计方法

介绍了sigma delta单环调制器的设计方法.详细阐述了如何把给定的要求转化为具体拓朴结构.通过该方法,设计者可以在仅知道精度要求的情况下,逐步实现所需要的电路结构,并通过-个三阶一位调制器的设计描述了这一流程.     

Delta Sigma调制器非理想因素建模

系统构建并研究了开关电容积分器DeltaSigma调制器非理想因素行为级模型.重点实现一种运放非线性直流增益模型,仿真表明它更有效反映奇次谐波失真,为保证模型真实性,综合考虑调制器其他非理想因素,如时钟抖动、量化器失配、采样噪声、开关非线性电阻以及运放参数(色化噪声、饱和电压、增益带宽、摆率等).     

A Direct Digital Synthesizer with Tunable Delta Sigma Modulator

In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma () modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the modulator is tuned according to the DDS output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. Two DDSs with tunable 1-bit D/A converters (real and complex) were designed and implemented on a programmable logic device (PLD); experimental results show their desired operation and performance.     

一种用于D类放大器的高阶单比特的SDM调制结构的实现

在介绍∑-△调制的基本原理基础上,重点设计出一种调制器结构,其特性适用于D类功放.分析了该电路结构特性对电路模块设计的影响,给出了电路模块的设计原则和指标.该结构最终测试结果为动态范围100 dB,信噪比90 dB,翻转频率400 kHz,总谐波失真0.008 4%.最后得到结论:在48 kHz,44.1 kHz采样率下该设计功能达到了预期效果,足以满足D类放大器应用.     

A Discretely Adaptive Delta Modulation Codec

A discretely variable slope delta modulation (DVSD) codec is described, which is suitable for integrated circuit realization. The step size is varied by a pulse number modulation method that does not require a precision digital-to-analog conversion circuit. An adaptation algorithm is discussed, taking into consideration the effect of transmission errors. The quantizer and integrator portion has been fabricated on a monolithic chip using MOS technology. Results obtained from an experimental 32 kbit/s codec demonstrate its excellent performance.     

适用于高阶Sigma Delta调制器的全差分运算放大器的设计

比较了套筒式共源共栅、折叠式共源共栅和两级AB类输出的三种运算放大器结构,提出了一种可用于前馈型高阶Sigma Delta调制器的全差分跨导运算放大器.采用SIMC 0.18 μmCMOS工艺,完成了含共模反馈电路的两级AB类输出的跨导运算放大器的设计.利用Cadence/Spectre仿真器进行仿真,结果表明放大器的直流增益为62.19dB,单位增益带宽为205.56 MHz,相位裕度为70.81°,功耗仅为0.42 mW,适合于低压低功耗Sigma Delta调制器的应用.     

A Second Order Multi-Bit Sigma Delta Modulator with Single-Bit Feedback

Multi-bit Sigma Delta modulators suffer from the DAC non-linearity problem and often need complicated Dynamic Element Matching (DEM) circuits. Combining a multi-bit quantizer and a single-bit DAC eliminates the need of DEM circuits, simplifies the design, and reduces the power consumption. Using a digital circuit to compensate the truncation error caused by cutting the multi-bit feedback to single-bit, the structure can achieve the same noise transfer function as a conventional multi-bit modulator. One drawback is that the signal scaling in such a structure lowers the overall resolution. In this paper the influence of signal scaling is analyzed and a design example given. A second order 3-bit modulator is fabricated in 0.35 m CMOS process, achieving 82 dB dynamic range at OSR = 128 and a peak SNDR of 73.1 dB.     

Sigma Delta调制器高效行为级建模

提出一种宏模型和Verilog-A模型相结合的方法对两阶、1位量化的Sigma Delta调制器进行建模.对调制器中的关键模块采用宏模型建模,对功能性模块采用Verilog-A描述.在Cadence环境下,基于华虹NEC 0.25μmCMOS工艺对模块进行设计和仿真,并与实际电路模块仿真结果和仿真时间进行对比,给出两种情况下调制器总体电路的SNR仿真结果.结果显示:这种建模方法既达到了较高的精度,又取得了较快的仿真速度.     

四阶前馈结构Sigma Delta调制器在SIMULINK建模

该文主要介绍了采用一种前馈的sigma delta调制器结构。与传统sigma delta调制器结构相比较,这种结构减少了系统对器件,尤其是积分器的非线性敏感性,使其内部信号的摆幅减小,降低了对运放的要求,提高了输入信号的幅度和频率。基于以上特点,把该种结构应用于低电压环境中。该文采用四阶结构,处理信号带宽达到50kHz,采样频率为12.8MHz,过采样率为128。经过Simulink建模仿真表明,输入幅度达到参考电压的0.77,输入频率为40kHz时,SNR达到118.4dB。     

设计Sigma-Delta A/D调制器结构

介绍Sigma Delta调制的基本原理。重点根据不同调制器结构的特性和产品的总体性能要求设计合适的调制器结构,实现其具体的电路总体结构,分析该电路结构特性对电路模块设计的影响,给出电路模块的设计原则和指标。芯片已在中芯国际0.18μm工艺线上流片成功,工作频率6.144 MHz,动态范围90 dB,信噪比88 dB,功耗9.4 mW,总谐波失真0.024 8%。     

A Delta Modulation Filter for Speech-Type Signals

This paper considers the realization of an all-digital system for direct filtering of a delta modulation (DM) encoded signal. We have shown [1] that this system can be realized fairly easily for any type of filter function when the signals are encoded with a linear DM. We now address the problem of digitally filtering an adaptive DM (ADM) encoded signal. We show that we can again realize any type of filter function and our system will operate directly on the ADM bit stream. In addition, we present a circuit realization that does not require complex digital hardware. Performance has been tested via simulation on a digital computer, using a variety of test signals; both temporal and spectral results are presented.     

Bandpass Delta Sigma A/D convertor using two-path multibit structure

The concept of an N-path bandpass Delta Sigma A/D convertor is introduced. A multibit sixth-order SC implementation is described. The new scheme appears to be very effective for the realisation of the narrowband bandpass delta-sigma modulators needed for communication applications.<>     

Noise Study of an Asynchronous Delta Sigma Modulator

The steady-state probability density function of the error of an asynchronous delta sigma modulator in the presence of a dc input and additive Gaussian noise withRCpower spectrum is obtained by solving the Fokker-Planck equation. The error pdf plots are presented for different system parameters.     

Design of Semi-Uniform Quantizers and Their Application in Sigma Delta A/D Converters

In this paper a new type of non-uniform quantizer, semi-uniform quantizer, is introduced. A k-bit semi-uniform quantizer uses the thresholds defined by a (k + 1)-bit uniform quantizer and arranges them in such a way that small-amplitude inputs will be quantized by small quantization steps and large-amplitude inputs by large quantization steps. Therefore the total quantization error power could be reduced and the modulator's dynamic range could be increased by 1-bit. The condition for a semi-uniform quantizer to achieve a better performance than a uniform quantizer is analyzed and verified using a second order 3-bit sigma delta modulator prototype chip, fabricated in 0.35 μm CMOS process. At 32× oversampling ratio the modulator achieves 81 dB dynamic range and 63.8 dB peak SNDR with 3-bit semi-uniform quantizer. With 3-bit uniform quantizer the dynamic range is 70 dB and the peak SNDR is 54.1 dB.     

Hybrid Companding Delta Modulation

We present a reasonably complete account of an improved adaptive delta modulation (ADM) system called hybrid companding delta modulation (HCDM). The HCDM system that is far superior to continuously variable slope DM (CVSD) or constant factor DM (CFDM) is advantageous, particularly for speech coding. It employs both syllabic and instantaneous companding schemes. Performance analysis of the system has been done and verified by computer simulation. In getting the mathematical formula for HCDM granular noise, a new method based on amplitude distribution is proposed. Optimization of the system parameter values by simulation is also discussed. In addition, an efficient method of hardware implementation is considered.     

A high-frequency double-sampling second-order /spl Delta//spl Sigma/ modulator

As the minimum feature size of VLSI technologies scales down, more of the signal processing tasks are performed in the digital domain. This results in increased speed, resolution, and dynamic range requirements for the analog-to-digital converter (ADC). High-speed and high-accuracy designs can be achieved by using oversampling ADC structures, which demand amplifiers with a high gain and a high unity-gain frequency. Due to the difficulty to meet both of these specifications, the ADC resolution at a frequency in the megahertz range appears to be limited by amplifier settling requirements. Design techniques to improve the ADC performance are presented. The proposed modulator structure uses the double-sampled technique, which increases by a factor of two the maximum speed of operation and correctly operates even with low dc gain amplifiers. Furthermore, the signal-to-noise ratio is significantly improved by a calibration stage, which dynamically estimates the offset errors to be removed by a simple subtraction from the output signal.