共查询到20条相似文献,搜索用时 15 毫秒
1.
Bergman J.I. Chang J. Joo Y. Matinpour B. Laskar J. Jokerst N.M. Brooke M.A. Brar B. Beam E. III 《Electron Device Letters, IEEE》1999,20(3):119-122
The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 106 VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit 相似文献
2.
This paper presents results of work to explore the feasibility of using resonant tunnelling diodes (RTDs) and conventional MOSFETs for the development of digital logic circuits. Based on the use of RTDs and MOSFETs, two different logic design styles—fixed pull-down and fixed pull-up—are proposed and evaluated. Fixed pull-up gates perform better than their CMOS counterparts with similar device sizes. Since the proposed fixed pull-down style avoids the use of series MOSFETs, for large fan-in gates it yields significantly better performance than the corresponding CMOS gates. 相似文献
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Haipeng Zhang Qiang Zhang Mi Lin Weifeng Lü Zhonghai Zhang Jianling Bai Jian He Bin Wang Dejun Wang 《半导体学报》2018,39(7):77-87
To improve the logic stability of conventional multi-valued logic (MVL) circuits designed with a GaN-based resonate tunneling diode (RTD),we proposed a GaN/InGaN/AlGaN multi-quantum well (MQW) RTD.The proposed RTD was simulated through solving the coupled Schrodinger and Poisson equations in the numerical non-equilibrium Green's function (NEGF) method on the TCAD platform.The proposed RTD was grown layer by layer in epitaxial technologies.Simulated results indicate that its current-voltage characteristic appears to have a wider total negative differential resistance region than those of conventional ones and an obvious hysteresis loop at room temperature.To increase the Al composite of AlGaN barrier layers properly results in increasing of both the total negative differential resistance region width and the hysteresis loop width,which is helpful to improve the logic stability of MVL circuits.Moreover,the complement resonate tunneling transistor pair consisted of the proposed RTDs or the proposed RTD and enhanced mode HEMT controlled RTD is capable of generating versatile MVL modes at different supply voltages less than 3.3 V,which is very attractive for implementing more complex MVL function digital integrated circuits and systems with less devices,super high speed linear or nonlinear ADC and voltage sensors with a built-in super high speed ADC function. 相似文献
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纳米电子器件RTD与CMOS电路结合,这种新型电路不仅保持了CMOS动态电路的所有优点,而且在工作速度、功耗、集成度以及电路噪声免疫性方面都得到了不同程度的改善和提高。文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟,并在此基础上对4×4阵列纳米流水线乘法器进行了结构设计。同时讨论了在目前硅基RTD器件较低的PVCR值情况下实现相应电路的可行性。 相似文献
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The basic building blocks for resonant tunneling diode (RTD) logic circuits are threshold gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, TGs can be implemented as efficiently as conventional ones, but realize more complex functions. Recently, RTD structures implementing multi-threshold threshold gates (MTTGs) have been proposed which further increase the functionality of the original TGs while maintaining their operating principle and allowing also the implementation of nanopipelining at the gate level. This paper describes the design of n-bit adders using these MTTGs. A comparison with a design based on TGs is carried out showing advantages in terms of power consumption and power delay product. 相似文献
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Yuh-Kuang Tseng Chung-Yu Wu 《Solid-State Circuits, IEEE Journal of》1999,34(1):68-79
New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications 相似文献
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Multivalued SRAM cell using resonant tunneling diodes 总被引:1,自引:0,他引:1
A multivalued SRAM cell using a vertically integrated multipeak resonant tunneling diode (RTD) pair is described. Two RTDs in series can have 2N+1 stable states. With this concept, a five-stable-state memory cell has been implemented with two 2-peak RTDs. Several designs are presented for a high-speed static random access multivalued memory using the folding characteristics of RTDs. The different designs are described and studied by comparing their power consumption under different conditions of device parameters and switching speed. The authors show that the proposed memory cell using a pair of multipeak RTDs yields the best result from the standpoint of size, power dissipation, and speed among the RTD memory cells discussed 相似文献
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Hong-Yi Huang Jing-Fu Lin 《Solid-State Circuits, IEEE Journal of》2004,39(8):1305-1312
This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(8):997-1007
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《Solid-state electronics》1996,39(10):1449-1455
We have developed a simple technology for monolithic integration of resonant tunneling diodes (RTDs) and heterostructure junction-modulated field effect transistors (HJFETs). We have achieved good device performance with this technology: HJFETs had transconductances of 290 mS/mm and current densities of 310 mA/mm for a 1.5 μm gate length; RTDs had room temperature peak to valley ratios greater than 20:1 with current densities of 42 kA/cm2. With this technology, we have demonstrated a monolithically integrated RTD + HJFET state holding circuit that can serve as a building block circuit for self-timed logic units. This circuit is resistor-free and operates at room temperature. The state holding circuit showed large noise margins of 1.21 V and 0.71 V, respectively, for input low and input high, for a 1.7 V input voltage swing. We have examined the transient response of the circuit and investigated the effect of circuit design parameters on propagation delay. We identify the RTD valley current as the limiting factor on propagation delay. We discuss the suitability of RTD + HJFET circuits such as our state holding circuit for highly dense integrated circuits. 相似文献
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Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1.2 μm MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates for moderate tree heights 相似文献
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《Microelectronics Journal》2014,45(11):1533-1541
Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP. 相似文献
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Due to the negative differential resistance exhibited by resonant tunneling diode (RTD), RTD is suited to implement the threshold gates and increases the functionality of a single gate. Recently, multi-threshold threshold gates (MTTGs) and generalized threshold gates (GTGs) have been proposed, which extend the circuit applications of RTDs. In this paper, a new RTD full adder structure with three logic modules is proposed. Based on this structure, four different adders are built with the combination of different module circuits based on MTTG and GTG. From the simulation results, one of the proposed circuits with GTG structure, namely FA_GG, has the best performance, which reduces 27.7–45.9% power-delay product value in comparison with the previous designs. 相似文献
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Vijay Kumar Sharma Manisha Pattanaik Balwinder Raj 《International Journal of Electronics》2013,100(2):200-215
Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node. 相似文献
18.
Ohtomo Y. Yasuda S. Togashi M. Ino M. Tanabe Y. Inoue J.-I. Nogawa M. Hino S. 《Solid-State Circuits, IEEE Journal of》1994,29(5):557-563
This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W 相似文献
19.
Ohkubo N. Suzuki M. Shinbo T. Yamanaka T. Shimizu A. Sasaki K. Nakagome Y. 《Solid-State Circuits, IEEE Journal of》1995,30(3):251-257
A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply 相似文献
20.
Low-power logic styles: CMOS versus pass-transistor logic 总被引:3,自引:0,他引:3
Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern 相似文献