Electromigration-induced failure in operando characterization of 3D interconnects: microstructure influence

An accurate knowledge of the phenomenon is required to develop a predictive modeling of the electromigration failure. Thus, a hitherto unseen SEM in operando observation method is devised. The test structure with “high density” through silicon vias (TSV) is tested at 623 K with an injected current density of 1 MA/cm². Regular shots of micrographs inform about the voids nucleation, forced in copper lines above the TSV, and about the scenario of their evolution. A clear relation is established between voids evolution and the one of the electrical resistance. The lack of impact of test conditions on the failure mechanism is demonstrated. Finally, the impact of microstructure on the depletion mechanism is discussed. Grain boundaries are preferential voids nucleation sites and influence the voids evolution. A probable effect of grain size and crystallographic orientation is revealed.     

Electromigration reliability of tungsten and aluminum vias andimprovements under AC current stress

The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region (<200 Hz) and four times the DC lifetime in the normal frequency region (> 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model     

Electromigration performance of Al–Si–Cu filled vias with titanium glue layer

Electromigration performance of vias filled with high temperature (480°C) sputtered Al alloys on Ti glue layers was investigated in comparison with W-stud vias. Electromigration lifetime and failure mode are quite different according to via structures and kinds of Al alloys used. Electromigration lifetime of W-stud via chain and Al–Cu filled via chain depends on the via to via distances, while that of Al–Si–Cu filled via chain does not depend on the via to via distances. Failure mode observations revealed that voids were formed only at a few locations in the test structure in Al–Si–Cu filled via chain while voids were formed at every via in W-stud via chains and Al–Cu filled via chains. It is supposed that Al moves through the Al–Si–Cu filled vias during electromigration test in spite of the existence of the Ti glue layer at the via bottom. The Al transportation, however, was prohibited at W-stud vias and Al–Cu filled vias. Glue Ti deposited at via bottom was converted to Al–Ti–Si alloy in Al–Si–Cu filled vias, while Al₃Ti alloy was formed at Al–Cu filled via bottom. It is speculated that Al transportation occurs through via bottom Al–Ti–Si alloy layer during electromigration test in the case of Al–Si–Cu filled vias.     

Application of selective CVD tungsten for low contact resistance via filling to aluminum multilayer interconnection

Process parameters for selective chemical vapor deposition of tungsten to fill vias between aluminum or aluminum alloy multilevel metallization have been identified and demonstrated. By controlling two competing parallel reactions: Aluminum and hydrogen reductions of tungsten hexafluoride in one reduction step process, the specific contact resistivity was found to be in the range of 2.5 to 8.0 x 10⁻⁹ ohm-cm² for 1.8 micron diameter vias. This is at least one order of magnitude lower than the values reported by the previous workers. It was also observed that alloying the aluminum did not appear to affect the contact resistance significantly. In this experiment one cold wall experimental reactor, two cold wall production systems of two different models and one hot wall tube furnace were used to deposit selective CVD tungsten on aluminum or aluminum with 1% silicon first level metal. As a consequence of these findings, problems associated with filling straight wall vias of high aspect ratio in VLSI multilevel interconnection (i.e., high contact resistance, poor step coverage, electromigration, etc.) can now be alleviated or resolved. Therefore, the use of selective CVD tungsten in the existing aluminum IC metallization becomes very attractive and feasible.     

使用氩离子击穿PVD阻挡层工艺提高90nm双大马真士革互联的参变量和可靠性

随着金属导线线宽的不断缩小,在90nm 技术以下,刻蚀残留物的存在会在应力迁移测试中形成高通孔电阻和空洞成核现象。物理氩离子预清洗是一种去除残留物的有效方法。但在应力迁移测试中发现,底部沟槽铜的二次溅射会导致器件的早期失效。反应性预清洗方法由于含有H +、H 类粒子而在减少C uO x 和清洗Si,N ,F,C ,O ,等蚀刻残留物时表现出其优越性。提出了针对传统PV D 工艺的反应性预清洗及PV D 击穿(沉积,刻蚀,沉积)工艺的解决方案。阻挡层击穿工艺减少了通孔电阻,提高了应力迁移性能,并通过薄钽沉积工序防止了铜的扩散从而保护了双嵌入斜面和错位通孔。此外,使电子阻塞和局部加热效应最小化的U 型界面,提高了电子迁移失效的平均时间,一致的、可重复的覆盖膜特性和良好的电参量测试结果已经证实了这种工艺的生产价值。     

The influence of TiN ARC thickness on stress-induced void formationin tungsten-plug vias

This paper describes a new failure mechanism in W-plug vias, and the process conditions which enhance it. For submicron technologies, the limiting factor in interconnect reliability performance is increasingly dominated by the electromigration resistance of tungsten-plug vias. We have observed that under certain experimental conditions, early electromigration failures can be induced in via-chain test structures. We have demonstrated that these are caused by stress-induced void formation in the metal line immediately beneath the tungsten plug. This is thought to be due to highly localized film stress around the base of the plug, which can be minimized by increasing the thickness of the TiN anti-reflective coating (ARC). This has the effect of reducing the incidence of early failure by suppressing the stress-induced failures     

Reliability assessment of multi-via Cu-damascene structures by wafer-level isothermal electromigration tests

In this paper, the isothermal wafer-level electromigration test method has been used to compare the resistance to electromigration damage of multi-level structures, realized by dual-damascene copper technology with a variable number of vias. “Upstream” and “downstream” structures have been defined, depending on the metal level where the line under test was located, with respect to the metal level where current and voltage taps were drawn. Not unexpectedly, the most critical current path for electromigration has been found in downstream structures, where the electron flow is entering the line under test. Worthy of note, a well defined dependence of the time to failure on the number of vias has been observed for these structures. Activation energy and current-density acceleration coefficient have been extracted and a quantitative relation is proposed to relate the lifetime expectancy to the number of vias.     

Electromigration failure distributions of dual damascene Cu /low – k interconnects

The reliability of dual damascene Cu/low – k interconnects is limited by electromigration – induced void formation at vias. In this paper we investigate via void morphologies and associated failure distributions at the low percentiles typical of industry reliability requirements. We show that Cu/low – k reliability is fundamentally limited by the formation of slit – voids under vias. Using experimental and simulation approaches we clarify the practical importance of apparent incubation phenomena associated with this failure mode.     

Electromigration: the time bomb in deep-submicron ICs

Electromigration results from the movement of metal ions as current flows through power wires in integrated circuits, causing voids and hillocks in the wires. The voids increase resistance or even cause opens in the wires, while hillocks can cause shorts to adjacent wires. This paper describes how electromigration is a ticking time bomb in IC designs, which can trigger a system failure at some undefined future time. The phenomenon is particularly likely to afflict the thin, tightly spaced power-distribution lines of deep-submicron designs     

三维叠层DRAM封装中硅通孔开路缺陷的模拟

采用硅通孔(TSV)技术的三维堆叠封装,是一种很有前途的解决方案,可提供微处理器低延迟,高带宽的DRAM通道.然而,在3D DRAM电路中,大量的TSV互连结构,很容易产生开路缺陷和耦合噪声,从而导致了新的测试挑战.通过大量的模拟研究.本文模拟了在三维DRAM电路的字线与位线中出现的TSV开路缺陷的故障行为,它作为有效...     

Circuit reliability simulator for interconnect, via, and contactelectromigration

A model for predicting Al interconnect and intermetallic contact/via electromigration time-to-failure under arbitrary current waveform is incorporated in a circuit electromigration reliability simulator. The simulator can (1) generate layout advisory for width and length of each interconnect, and the number of contacts and vias at each node in a circuit, and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure as functions of time, temperature, voltage, frequency, and previous stress (e.g., burn-in)     

Morphology of electromigration-induced damage and failure in Al alloy thin film conductors

Distinct morphologies of electromigration-induced voids and failures are shown for Al, Al-2%Cu, and Al-2%Cu-l% Si narrow (1–6 μm) unpassivated thin film conductors. SEM and TEM images typically show large non-fatal voids and narrow slit-like open circuit failures for all film conditions and accelerated test conditions. Evidence for transgran-ular slit failures is shown for 1.33 μm wide conductors. A simple model for void growth is presented which accounts for the void morphologies seen. The observed morphologies and the results of void growth modelling suggest that slit voids nucleate after other voids and rapidly produce failure. These conclusions are discussed in terms of ‘classical’ models for electromigration failure processes and resistance and noise power monitoring techniques.     

Investigation of the effects of byproduct components in Cu plating for advanced interconnect metallization

This paper discusses the effects of byproduct components generated from a commercially available two components additive package on the copper plating performance for advanced interconnect metallization. The increase in accumulative breakdown products from the sulfur-containing type-A additive during the electroplating (ECP) process, measured using high performance liquid chromatography (HPLC), showed a detrimental effect on via fill performance. These vias with voids may fail by open circuit sooner due to electromigration. Besides, increase of in-film sulfur content was found from the analysis of secondary-ion mass spectrometry (SIMS) on the film electroplated using heavily used plating solution. It was suggested that the increase of incorporated sulfur impurities could render in slower self-annealing rate of the as-plated copper film due to the grain boundary pinning effect.     

Combined low-frequency noise and resistance measurements for void extraction in deep-submicrometer interconnects

Electromigration stress can give rise to voids that increase the resistance and localized thermal stress in interconnects. Estimation of the extent of voiding can provide information on the material quality and the amount of degradation that has resulted from the electrical stress. In this paper, a model is proposed that can be used to estimate the effective void volume in deep-submicrometer interconnects. The model uses a combination of low-frequency noise and resistance measurements, and also considers the thermal coefficient of resistance in calculating the change in resistance of the interconnect line. A deconvolution scheme was employed to extract the 1/f noise component from the noise-measurements to improve the accuracy of the extraction algorithm. To verify the accuracy of the model, the focused ion beam (FIB) technique was used to mill holes (to simulate voids) of known dimensions. The model was further applied to an electromigration stress study of aluminum (Al) interconnects as a method of testing its validity for stress-induced voids. The proposed technique is a useful reliability tool for void detection in deep-submicrometer interconnects.     

Correlation of electromigration lifetime distribution to failure mode in dual Damascene Cu/SiLK interconnects

The electromigration cumulative percent lifetime probability of dual Damascene Cu/SiLK interconnects was fitted using three, individual lognormal functions where the functional populations were grouped by void growth location determined from focused ion beam failure analysis of all 54 of the stressed structures. The early, first mode failures were characterized by small voids in the bottom of the vias. The intermediate mode failures had voids in the line and via bottom while the late mode failures had voids that formed in the line only. The three, individual lognormal functions provided good fits of the data. Failure mode population separation using comprehensive failure analysis suggested that only the first mode failures should be used in the prediction of the chip design current.     

Thermal characteristics of submicron vias studied by scanning Jouleexpansion microscopy

Thermal characteristics of submicron vias strongly impact reliability of multilevel VLSI interconnects. The magnitude and spatial distribution of the temperature rise around a via are important to accurately estimate interconnect lifetime under electromigration (EM), which is temperature dependent. Localized temperature rise can cause stress gradients inside the via structures and can also lead to thermal failures under high current stress conditions, such as electrostatic discharge (ESD) events. This letter reports the first use of a novel thermometry technique, scanning Joule expansion microscopy, to study the steady state and dynamic thermal behavior of small geometry vias under sinusoidal and pulsed current stress. Measurement of the spatial distribution of temperature rise around a submicron via is reported with sub-0.1 μm resolution, along with other thermal characteristics including the thermal time constant     

Hybrid punch through approach to address electroless related integration issues of hybrid CoWP/SiCN barriers

Integration of CoWP self-aligned barriers in hybrid stack with SiCN liner in a standard 65 nm technology node integration scheme faces several issues. For example, bowing of upper metal level occurs due to the interaction between CoWP and etch plasma during SiCN opening step leading to lower line resistance compared to SiCN reference. Furthermore, wet cleaning after patterning step must be carefully processed in order to remove residues while keeping CoWP integrity. Electrical and reliability performance show that a clean recipe can be efficient to remove residues leading to low via resistance but in the same time, no electromigration improvement compared to SiCN reference is observed due to CoWP degradation and vice versa. To overcome integration issues, a new integration scheme called hybrid punch through (HPT) approach is proposed. In this approach, the patterning step is modified by SiCN open removal and it is followed by an adapted punch through process during metallization to open the via. HPT approach allows avoiding contact between CoWP and etch plasma or cleaning chemistry and leads to better electrical performance in terms of via and line resistances compared to standard scheme without degrading CoWP.     

The influence of addition elements on the early resistance changes observed during electromigration testing of Al metal lines

This paper provides a critical review on early resistance changes observed during electromigration testing of Al, AlSi and AlSiCu metal lines. At present, high resolution in situ electrical resistance measurements are widely accepted as a valuable tool for the study of electromigration. It will be shown however that the results of these measurements should be interpreted with care. It will indeed be shown that, particularly for Si and/or Cu alloyed metallizations, an early resistance change measurement (during electromigration) can contain information that has no link with the damage induced by the electromigration process. A number of disturbing factors will be identified, which are all induced by temperature driven processes. The first type of disturbance is well known: the immediate change of the measured resistance with temperature steps and fluctuations (thermometer effect). The second type of disturbance is not so widely recognised. It is induced by time dependent changes that are observed over an extended period of time, following a preceding temperature step. Two types of disturbing contributions to resistance changes of this second type are identified, which will be denoted as irreversible changes and reversible changes. The irreversible resistance changes are usually observed during the first annealing of the metal line. The reversible changes are typically detected at the start of an electromigration measurement, when the current stress is switched on. It is shown that both the reversible and irreversible changes are caused by precipitation/dissolution reactions of addition elements. It is also shown that the often observed parabolic initial resistance increase that is detected at the start of electromigration experiments should be attributed to the time dependent, reversible dissolution of the addition element(s). Comparable experiments, executed however at a much reduced current level so that no Joule heating takes place, and hence no reversible processes are initiated, show that the kinetics of the purely electron-wind induced resistance changes are completely different: instead of a parabolic initial increase, an incubation time can be observed during the first stage of the measurement.     

Electromigration characteristics of tungsten plug vias under pulseand bidirectional current stressing

Using Kelvin test structures, electromigration performances of selective CVD tungsten filled vias under DC, pulsed DC, and AC current signals have been studied. The metallization consists of Al-Cu/TiW multilevel metals. The via electromigration lifetime exhibits a current polarity dependence. The via AC lifetimes are found to be much longer (more than 1000×) than DC lifetimes under the same peak stressing current density. The via lifetimes under pulsed DC stress of 50% duty factor are twice the DC lifetimes at low-frequency regions (<200 Hz) and 4-5 times the DC lifetimes at high-frequency regions (>10 kHz). The results are in agreement with the vacancy relation model     

Comparative study on the effect of misalignment on bordered and borderless contacts

Continued shrinking of feature sizes in integrated circuits has raised increasing reliability concern. In order to achieve higher packing density, interconnects are migrating toward borderless contacts and vias. The penalty with the absence of metal extension, however, is the decrease in electromigration lifetimes. The issue is particularly critical when there is a misalignment between the contact and metal line, which may occur due to process variability. In this paper, we studied the effect of misalignment on the electromigration lifetimes for bordered and borderless contacts. We found that the misalignment effect becomes more pronounced in borderless contacts. We also studied the case of multiple contact configuration. The results indicate that electromigration lifetimes increase with increasing number of contacts in series. The experimental data is consistent with finite element modeling results.