Application of coupled electro-thermal and physics-of-failure-based analysis to the design of accelerated life tests for power modules

In the reliability theme a central activity is to investigate, characterize and understand the contributory wear-out and overstress mechanisms to meet through-life reliability targets. For power modules, it is critical to understand the response of typical wear-out mechanisms, for example wire-bond lifting and solder degradation, to in-service environmental and load-induced thermal cycling. This paper presents the use of a reduced-order thermal model coupled with physics-of-failure-based life models to quantify the wear-out rates and life consumption for the dominant failure mechanisms under prospective in-service and qualification test conditions. When applied in the design of accelerated life and qualification tests it can be used to design tests that separate the failure mechanisms (e.g. wire-bond and substrate-solder) and provide predictions of conditions that yield a minimum elapsed test time. The combined approach provides a useful tool for reliability assessment and estimation of remaining useful life which can be used at the design stage or in-service. An example case study shows that it is possible to determine the actual power cycling frequency for which failure occurs in the shortest elapsed time. The results demonstrate that bond-wire degradation is the dominant failure mechanism for all power cycling conditions whereas substrate-solder failure dominates for externally applied (ambient or passive) thermal cycling.     

An improved reliability model for Si and GaN power FET

The existing standard reliability models for power devices are not satisfactory and they fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is mainly attributed to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods relay on the acceleration of one dominant failure mechanism. Recently, device reliability research programs are aimed to develop new theoretical models and experimental methods that would result a better assessment of the device lifetime as well as point out on the dominating failure mechanism for particular operating conditions. A new model, named Multi failure mechanism, Overstress Life test (MOL) has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions in advanced FPGA devices (for 45 and 28 nm technologies). In this work we present, for the first time, the implementation of the MOL model to investigate the reliability of silicon power MOSFET and GaN power FET devices. Both, LTSpice simulation and experimental data are presented for a test circuit of a ring oscillator, based on CMOS-FET, NMOS-FET, PMOS-FET and N-channel e-GaN FET. The monitored data was acquired in-situ in form of the ring frequency or Vds values that enabled to assess the lifetime and determine the dominating mechanism during accelerated wearout by temperature, applied bias voltage, thermal cycling, gamma and electron irradiation. Moreover, in the case of GaN devices, RDS-On monitoring circuit has also been operated during thermal cycling of the tested component and the acceleration factor was derived for various operational parameters.     

An overview of the reliability prediction related aspects of high power IGBTs in wind power applications

Reliability is becoming more and more important as the size and number of installed Wind Turbines (WTs) increases. Very high reliability is especially important for offshore WTs because the maintenance and repair of such WTs in case of failures can be very expensive. WT manufacturers need to consider the reliability aspect when they design new power converters. By designing the power converter considering the reliability aspect the manufacturer can guarantee that the end product will ensure high availability. This paper represents an overview of the various aspects of reliability prediction of high power Insulated Gate Bipolar Transistors (IGBTs) in the context of wind power applications. At first the latest developments and future predictions about wind energy are briefly discussed. Next the dominant failure mechanisms of high power IGBTs are described and the most commonly used lifetime prediction models are reviewed. Also the concept of Accelerated Life Testing (ALT) is briefly reviewed.     

System-level reliability assessment of mixed-signal convergent microsystems

The next-generation convergent microsystems, based on system-on-package (SOP) technology, require up-front system-level design-for-reliability approaches and appropriate reliability assessment methodologies to guarantee the reliability of digital, optical, and radio frequency (RF) functions, as well as their interfaces. Systems approach to reliability requires the development of: i) physics-based reliability models for various failure mechanisms associated with digital, optical, and RF Functions, and their interfaces in the system; ii) design optimization models for the selection of suitable materials and processing conditions for reliability, as well as functionality; and iii) system-level reliability models understanding the component and functional interaction. This paper presents the reliability assessment of digital, optical, and RF functions in SOP-based microsystems. Upfront physics-based design-for-reliability models for various functional failure mechanisms are presented to evaluate various design options and material selection even before the prototypes are made. Advanced modeling methodologies and algorithms to accommodate material length scale effects due to enhanced system integration and miniaturization are presented. System-level mixed-signal reliability is discussed thorough system-level reliability metrics relating component-level failure mechanisms to system-level signal integrity, as well as statistical aspects.     

The reliability of laser diodes and laser transmitter modules

This paper reviews the reliability of laser transmitter modules for use in optical fibre transmission systems. Methods for reliability testing and lifetime prediction are discussed and the dominant failure mechanisms affecting laser modules are described. The current status of laser module reliability is discussed, based on both published results, and on the findings of a study at BT Laboratories of the reliability of commercial laser modules from ten manufacturers. It is concluded that significant progress has been made in the reliability of laser diodes, through the understanding of basic failure mechanisms, leading to long predicted lifetimes for a number of different laser structures. However, module packaging is less reliable and further work is required to identify and eliminate those materials and processing technologies which lead to the risk of early failure.     

Optimal design of k-out-of-n:G subsystems subjected to imperfect fault-coverage

Systems subjected to imperfect fault-coverage may fail even prior to the exhaustion of spares due to uncovered component failures. This paper presents optimal cost-effective design policies for k-out-of-n:G subsystems subjected to imperfect fault-coverage. It is assumed that there exists a k-out-of-n:G subsystem in a nonseries-parallel system and, except for this subsystem, the redundancy configurations of all other subsystems are fixed. This paper also presents optimal design polices which maximize overall system reliability. As a special case, results are presented for k-out-of-n:G systems subjected to imperfect fault-coverage. Examples then demonstrate how to apply the main results of this paper to find the optimal configurations of all subsystems simultaneously. In this paper, we show that the optimal n which maximizes system reliability is always less than or equal to the n which maximizes the reliability of the subsystem itself. Similarly, if the failure cost is the same, then the optimal n which minimizes the average system cost is always less than or equal to the n which minimizes the average cost of the subsystem. It is also shown that if the subsystem being analyzed is in series with the rest of the system, then the optimal n which maximizes subsystem reliability can also maximize the system reliability. The computational procedure of the proposed algorithms is illustrated through the examples.     

Simulation of electrical overstress thermal failures in integratedcircuits

Electrical overstress (EOS) and electrostatic discharge (ESD) pose the most dominant threats to integrated circuits (ICs) reliability. As a measure for EOS/ESD reliability, the power-to-failure versus time-to-failure relationship (power profile) has been recently proposed to determine the EOS failure thresholds of integrated circuits. This paper presents a nonlinear mixed 2D-1D thermal simulator, iTSIM, for ESD/EOS failure studies in ICs. iTSIM's computational efficiency to handle large-scale EOS thermal problems in ICs derives from the special set of boundary conditions introduced in this paper. Simulated power profiles for various combinations of major thermal parameters of the IC die-package structure are shown to agree with experimental data     

高可靠DC-DC混合电源长寿命评价技术研究

随着科学技术的发展、设计和制造水平的大幅度提高,高可靠长寿命DC-DC混合电源产品在军事及航空航天领域应用越来越广泛,如何预测其寿命是值得深入研究的重要问题。采用加速退化试验方法,对一款高可靠DC-DC混合电源进行可靠性评价与寿命预测。此研究成果对解决高可靠性电源产品的可靠性保证和寿命预测问题具有很好的工程意义。     

Synthesis of Fault Trees: An Example of Noncoherence

The Lapp & Powers (L&P) fault-tree model of a nitric acid cooling process is explored to a greater level of depth than in the previous round-robin correspondence on the controversy over exclusive-or (XOR) gate G7 in the L&P fault tree. In this paper, the minimalized logic equations for success or failure of G7 are derived, and the subsystem reliability function is calculated. The subsystem reliability vs component reliability function is U-shaped; this is not an abnormality, but a result of the XOR failure logic. The overall system reliability vs component reliability function, however, is J-shaped. Some further comments are made on the relevance of this problem to the study of s-noncoherent and fail-safe systems.     

Reliability Evaluation and Prediction for Discrete Semiconductors

The use of accelerated step-stress and constant stress-in-time test techniques is demonstrated for generating models for predicting reliability at use conditions. Reliability prediction models were obtained for a signal diode, signal and power transistors, silicon trolled rectifier, and metal oxide varistor. Each of these device types follows the Arrhenius model for reliability prediction. Techniques are demonstrated for determining 1) the acceleration factor between extremely high acceleration testing conditions and field operating conditions on the signal diode; and 2) the acceleration or multiplying factor between high level stresses and use conditions which can be used to predict the performance of the signal diode over time. The effect of relative humidity on reliability is discussed. Devices under power operation have a lower relative humidity (RH) than the environment. This low RH suppresses humidity activated mechanisms. A transistor high-reliability screen which removes devices with early manufacturing type defects is described. This screen was effective, efficient and economical for improving the reliability of systems. A technique of combining acceleration factors for a number of items which affect reliability was demonstrated for the diode. This same technique should be useful for most device reliability predictions. The acceleration factors, however, can not be extrapolated into stress levels much above maximum ratings where new failure modes may appear that override the established failure rate relation with stress. The straight line plots of failure rates in this paper are terminated before these threshold limits.     

Bayesian Confidence Limits for the Reliability of Mixed Cascade and Parallel Independent Exponential Subsystems

This paper deals with the theoretical problem of derving Bayesian confidence intervals for the reliability of a system consisting of both cascade and parallel subsystems where each subsystem is independent and has an exponential failure probability density function (pdf). This approach is applicable when test data are available for each individual subsystem and not for the enfire system. The Mellin integral transform is used to analyze the system in a step-by-step procedure until the posterior pdf of the system reliability is obtained. The posterior cumulative distribution function is then obtained in the usual manner by integrating the pdf, which serves the dual purpose of yielding system reliability confidence limits while at the same time providing a check on the accuracy of the derived pdf. A computer program has been written in FORTRAN IV to evaluate the confidence limits. An example is presented which uses the computer program.     

MOS VLSI reliability and yield trends

The yield and reliability capability of an MOS technology are shown to be the product of at least six different technological trends; namely those towards: 1) more complex device structures, 2) scaled down feature sizes, 3) increased wafer sizes, 4) factory automation, 5) increased die size and package lead counts, and 6) increasingly sophisticated computer-aided design tools. The capabilities of a specific technology are a function of the equipment and processes by which it is manufactured and these are often the rate-limiting factors for evolution to the next generation of technology. However, because of the impact of scaling trends on MOS IC failure mechanisms, reliability concerns are starting to dominate the rate of technology change. This is evidenced, even at the present, by the fact that technology decisions must be made by trading off one reliability failure mechanism against another. For example, the high storage charge density needed to provide strong signals for alpha-particle-induced soft error immunity, produces high electric fields and oxide breakdown problems in thin-oxide MOS storage capacitors. Failure distribution for both failure mechanisms are shown to be exponentially dependent (in an inverse manner) on the scale factor for oxide thickness. Hot-electron degradation is also exponentially dependent on the scale factor for channel length. Metal and contact electromigration lifetimes can be reduced by the seventh and nineth powers of scale factor, respectively. The implications are that the dominant reliability mechanisms may change in the future, and that wearout will start to impinge on reliability life.     

Selected failure mechanisms of modern power modules

This paper reviews the main failure mechanisms occurring in modern power modules paying special attention to insulated gate bipolar transistor devices for high-power applications. This compendium provides the main failure modes, the physical or chemical processes that lead to the failure, and reports some major technological countermeasures, which are used for realizing the very stringent reliability requirements imposed in particular by the electrical traction applications.     

Fully integrated electrothermal multidomain modeling of RF MEMS switches

RF MEMS switches have demonstrated excellent performance. However, before such switches can be fully implemented, they must demonstrate high reliability and robust power-handling capability. Numerical simulation is a vital part of design to meet these goals. This paper demonstrates a fully integrated electrothermal model of an RF MEMS switch which solves for RF current and switch temperature. The results show that the beam temperature increases with either higher input power or increased frequency. The simulation data are used to predict switch failure due to temperature-related creep and self pull-in over a wide range of operating frequency (0.1-40 GHz) and power input (0-10 W). Self pull-in is found to be the dominant failure mechanism for an example geometry.     

Reliability physics of compound semiconductor transistors for microwave applications

This paper reviews the reliability problems of compound semiconductor transistors for microwave applications. These devices suffer from specific failure mechanisms, which are related to their limited maturity, with the exception of the GaAs MESFETs, which exhibit a stable technology and an assessed reliability. The metallizations employed in high electron mobility transistors (HEMTs) already benefit from this assessment. However, HEMT are affected by concerns related to hot carriers and impact ionization. The trapping of carriers and the generation of defects in the different layers are responsible for the observed instabilities. The stability of the base dopant is the main reliability concern for heterojunction bipolar transistors (HBTs). Beryllium outdiffuses from the base into the emitter and causes device degradation. Carbon has a lower diffusivity, but is affected by the presence of hydrogen, which prompts gain variations. Finally the hot carriers reliability concern in SiGe HBTs is briefly reviewed.     

微电子工艺技术可靠性

对工艺过程进行评估的目的在于找出存在可靠性缺陷的地方，它是针对技术磨损的机理，通过对专门设计的测试结构进行封装级或圆片级可靠性测试，获取可靠性模型参数和可靠性信息，超大规模集成电路主要的三个的失效机理分别是热载流子注入效应，金属化电迁移效应和氧化层的TDDB击穿，本文对这三种失效机理分别进行了介绍，对各自对应的可靠性模型进行了说明，列举了热载流子汪入效应的寿命评价实例，说明了可靠性评价的重要性，给出了可靠性主人在工艺中的应用流程图。     

基于加速性能退化试验的板级可靠性评估

传统的可靠性评估方法一般基于失效寿命数据,而目前对于高可靠长寿命的电子产品,很难通过加速试验获得其失效寿命时间。为解决这一矛盾,将性能退化理论引入到传统可靠性评估中,提出了基于失效数据及加速性能退化的可靠性评估的新方法。应用某型雷达24V/2A稳压电源板加速性能退化试验进行验证,结果表明该方法用于高可靠长寿命电子装备的可靠性评估是正确有效的。     

Power saving modes in modern microcontroller design, diagnostics and reliability

This paper is targeting some of the most important problems in modern microcontroller-on-chip design: low power consumption, efficient chip diagnostics and design reliability. A case study of a microcontroller device is presented. Applied system-level techniques for dynamic power saving are described. Chip diagnostic methods are developed that are based on measuring of the supply current in different power saving modes. Special attention is also paid to design reliability issues. The device reliability limits are tested on both manufacturing and electrical stress failure mechanisms.     

A combined fuzzy-logic and physics-of-failure approach toreliability prediction

An original reliability prediction procedure is presented. The physics of failure accounts for the failure mechanisms involved (a lognormal distribution was presumed); the interactions (synergies) between the technology factors depending on the manufacturing techniques are considered. The basis of this methodology (called SYRP=synergetic reliability prediction) is the assessment of failure-risk coefficients (FRC), based on fuzzy logic, for the potential failure mechanisms induced at each manufacturing step. These FRC are corrected at the subsequent steps by considering the synergy of the manufacturing factors, At the end of the manufacturing process, final FRC are obtained for each potential failure mechanism; the parameters of the lognormal distribution are calculated with a simple algorithm. Experimental results for four lots of the same type of semiconductor devices, each lot being manufactured with a slightly different technology, were obtained. SYRP forecasts for these four lots agree well with accelerated life test results. This is a fairly good result, because SYRP was used early, at the design phase     

A separable method for incorporating imperfect fault-coverage intocombinatorial models

This paper presents a new method for incorporating imperfect FC (fault coverage) into a combinatorial model. Imperfect FC, the probability that a single malicious fault can thwart automatic recovery mechanisms, is important to accurate reliability assessment of fault-tolerant computer systems. Until recently, it was thought that the consideration of this probability necessitated a Markov model rather than the simpler (and usually faster) combinatorial model. SEA, the new approach, separates the modeling of FC failures into two terms that are multiplied to compute the system reliability. The first term, a simple product, represents the probability that no uncovered fault occurs. The second term comes from a combinatorial model which includes the covered faults that can lead to system failure. This second term can be computed from any common approach (e.g. fault tree, block diagram, digraph) which ignores the FC concept by slightly altering the component-failure probabilities. The result of this work is that reliability engineers can use their favorite software package (which ignores the FC concept) for computing reliability, and then adjust the input and output of that program slightly to produce a result which includes FC. This method applies to any system for which: the FC probabilities are constant and state-independent; the hazard rates are state-independent; and an FC failure leads to immediate system failure