Field programmable gate arrays in space

The use of field programmable gate arrays (FPGAs) in satellite and other spacecraft is on the rise. They are increasingly competitive when compared to traditional application-specific integrated circuits (ASICs). However, exposure to space radiation produces the same physical effects on both FPGAs and ASICs. How these radiation effects can translate to circuit malfunctions and how these problems can be prevented or mitigated is a complex, multifaceted issue that depends on the specific technology and the device's internal architecture. First and foremost, designers should implement a reliable ASIC/FPGA development methodology for the definition, design, verification, physical implementation and validation phases of any ASIC/FPGA to be flown as part of the spacecraft platform or critical payload. This should be contractually enforced. The European Space Agency (ESA) will continue to make available its own internal standard or any other equivalent methodology proposed by the contractor. As soon as the new ECSS standard on this subject is available, ESA will start using it as an applicable document in all projects where ASICs or FPGAs are to be developed.     

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.     

采用标准单元库和阵列方法的混合模拟／数字ASIC设计

用标准单元库和阵列方法进行混合电路的设计只有五、六年的历史。它们具有数字半定制芯片集成度高、速度快、功耗低的优点。但由于精度差、分辨率低,混合模拟数字电路的使用受到了限制。最近,由于先进的工艺技术和设计手段的出现,使得高性能混合模拟/数字ASIC成为可能,并将成为今后集成电路的主要方向之一。本文从单元库的建立、阵列结构、性能模拟诸方面综述了混合模拟/数字ASIC的设计进展。     

FPGA与ASIC之兼容设计

为了利用FPGA和ASIC设计各自的优点,很多设计首先通过FPGA来实现,再根据需求转换成ASIC实现,同时更多的ASIC设计为了降低风险和成本,在设计过程中会选择使用FPGA进行功能验证。这就需要设计能在两者之间互相转换,怎样使电路设计以最快的速度、最小的代价来满足这一转换,本文提出了一些兼容设计方法,并进行了分析,最后给出了兼容设计实例,设计实践表明这些设计方法对FPGA与ASIC的兼容设计是行之有效的。     

FPGAs achieve superior speed and density with antifuse advancements

FPGAs based on low-resistance, low-capacitance “antifuse” programmable elements offer very high-speed performance with small, cost-effective die sizes for high-volume production applications. FPGA vendors continue to invest in this technology to push further into the performance and density/cost realm previously dominated by conventional mask programmed ASICs. These high-performance, high-density antifuse based products will further distance themselves in speed, cost, and ease-of-use from slower, more costly RAM-based FPGAs.     

超高速移位寄存器单元结构设计方法

本文以高速八位移位寄存器的研制为例,介绍了一种简便可行的专用集成电路单元结构设计方法。专用集成电路的设计目前有很多方法,但都基于有先进的设计工具和较为丰富的集成电路CAD库。没有这些设计环境,使用单元结构设计方法同样可以较快地设计专用集成电路。与通常的设计相比,这种方法具有设计周期短,电路性能高,设计成本低,版图布局对称等特点,是一种较好的专用集成电路设计方法。     

Routability of Network Topologies in FPGAs

A fundamental difference between application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used. In this paper, we investigate how well several common network topologies map onto a modern FPGA routing fabric. Different multiprocessor network topologies with between 8 and 64 nodes are mapped to a single large FPGA. Except for the fully-connected networks, it is observed that the difference in logic resources used and routing overhead among these topologies is insignificant for the systems tested. Fully-connected networks up to about 22 nodes are also feasible on the same FPGA although the logic and routing utilization clearly grows much faster. The conclusion is that a modern FPGA fabric is very rich in resources and capable of supporting highly interconnected topologies. For systems with a modest number of nodes implemented on current large FPGAs, it is not necessary to use the connectivity-limited topologies typically used for networks-on-chip. Rather, direct point-to-point connections between all communicating nodes can be considered.     

FPGA在ASIC设计流程中的应用

本文介绍了FPGA器件在ASIC芯片开放中的应用,通过仿ASIC的FPGA在系统验证板在实际硬件环境中的验证可以弥补ASIC设计流程中仿真的不足,通过该验证也可以加快ASIC设计且降低由于逻辑问题所造成ASIC开发中的成本损耗。     

Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA

Programmable devices are an interesting alternative when implementing embedded systems on a low-volume scale. In particular, the affordability and the versatility of SRAM-based FPGAs make them attractive with respect to ASIC implementations. FPGAs have thus been used extensively and successfully in many fields, such as implementing cryptographic accelerators. Hardware implementations, however, must be protected against malicious attacks, e.g. those based on fault injections. Protections have been usually evaluated on ASICs, but FPGAs can be vulnerable as well. This work presents thus fault injection attacks against a secured AES architecture implemented on a SRAM-based FPGA. The errors are injected during the computation by means of voltage glitches and laser attacks. To our knowledge, this is one of the first works dealing with dynamic laser fault injections. We show that fault attacks on SRAM-based FPGAs may behave differently with respect to attacks against ASIC, and they need therefore to be addressed by specific countermeasures, that are also discussed in this paper. In addition, we discuss the different effects obtained by the two types of attacks.     

Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA

An Application Specific Inflexible FPGA (ASIF) is a modified form of an FPGA which is designed for a predefined set of applications that operate at mutually exclusive times. An ASIF is a compromise between FPGAs and Application Specific Integrated Circuits (ASICs). Compared to an FPGA, an ASIF has reduced flexibility and improved density while compared to an ASIC, it has larger area but improved flexibility. This work presents a new homogeneous tree-based ASIF and uses a set of 16 MCNC benchmarks for experimentation. Experimental results show that, on average, a homogeneous tree-based ASIF gives 64% area gain when compared to an equivalent tree-based FPGA. Further, the experiments are performed to explore the effect of look-up table (LUT) and arity size on a tree-based ASIF. Later, comparison between tree and mesh-based ASIF is performed and results show that tree-based ASIF is 12% smaller in terms of routing area and consumes 77% less wires than mesh-based ASIF. Finally the quality comparison between two ASIFs reveals that, on average, tree-based ASIF gives 33% area gain as compared to mesh-based ASIF.     

Buffering global interconnects in structured ASIC design

Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This paper proposes a novel and accurate statistical estimation technique for distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the buffer distribution estimation is accurate and economic, and that a uniform buffer distribution can maintain a high degree of regularity in design and shows a good timing performance, comparable with nonuniform buffer distribution.     

从FPGA到ASIC的风险与对策

由于FPGA的种种优点,越来越多的电子设计师在初次设计电子产品时选择FPGA来完成电路的prototype设计。然后,再在必要时将prototype设计从FPGA转换成ASIC。在此转换过程中有一定的风险,如ASIC电路的复位、时钟树的设计、封装形式的选择以及可测性设计等。文中讨论了这些风险,并给出了减少这些风险的解决方案。     

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.     

FPGA和ASIC设计特点及应用探讨

介绍了ASIC、FPGA的设计步骤和设计流程,重点比较两者之间的设计特点和应用趋向,采用这两种不同方法完成40G高阶数字交叉连接芯片设计.通过比较表明:FPGA技术适用于小批量、产品更新快、周期短的电子产品设计,可以明显提高设计速度,缩短产品上市时间;ASIC技术适用于大批量、产品比较成熟、生命周期长的电子产品设计.ASIC的集成度和单片价格都比FPGA有优势.     

DSP system integration and prototyping with FPGAS

Field Programmable Gate Arrays (FPGAs) offer a cost-effective and flexible technology for DSP ASIC prototype development. In this article, the fast ASIC prototyping concept based on the use of multiple FPGAs is reviewed in different engineering applications. The design experiences of the proposed approach, applied to four different DSP ASIC design projects are presented. The design experiences concerning the selection of the design methodology, application architectures and prototyping technologies are analyzed with respect to efficient system integration and ASIC migration from the FPGA prototype onto first-time functional silicon. Novel prototyping techniques based on using configurable hardware modellers concerning the same objective are studied. Some future goals are outlined to develop an integrated, multipurpose DSP ASIC prototyping environment.     

FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures

Physically Unclonable Functions (PUFs) are a promising technology and have been proposed as central building blocks in many cryptographic protocols and security architectures. Among other uses, PUFs enable chip identifier/authentication, secret key generation/storage, seed for a random number generator and Intellectual Property (IP) protection. Field Programmable Gate Arrays (FPGAs) are re-configurable hardware systems which have emerged as an interesting trade-off between the versatility of standard microprocessors and the efficiency of Application Specific Integrated Circuits (ASICs). In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. PUF technology can protect the individual FPGA IP cores with less overhead. In this article, we first provide an extensive survey on the current state-of-the-art of FPGA based PUFs. Then, we provide a detailed performance evaluation result for several FPGA based PUF designs and their comparisons. Subsequently, we briefly report on some of the known attacks on FPGA based PUFs and the corresponding countermeasures. Finally, we conclude with a brief overview of the FPGA based PUF application scenarios and future research directions.     

FPGA vs. ASIC for low power applications

Field Programmable Gate Array (FPGA) are becoming more and more popular and are used in many applications. However, it is well known that the performance is limited comparing to full ASIC implementation, but for many applications the speed requirements fit the ones provided already by existing FPGA circuits. Power consumption seems to be one of the most important limiting factor and so far it is in favour of Application Specific Integrated Circuits (ASIC) [Varghese Georges, Jan M. Rabaey, Low-Energy FPGA, Architecture and Design, Kluwer Academic Publishers, 2001; Tadahiro Kuroda, Power-Aware Electronics: Challenges and Opportunities, Tutorial at FTFC 2003, Paris, May 2003]. In this paper, we will present results obtained by characterizing various circuits implemented using both FPGA and ASIC technologies in order to determine the power consumption ratio and evaluate the efficiency of the power optimization techniques such as clock gating [Amara AMARA, Philippe Royannez, VHDL for Low Power, (Chapter 11), Low Power Electronics Design, Edited by Christian Piguet, CRC Press 2005; Luca Benini, Giovanni De Micheli, Dynamic Power Management, Kluwer Academic Publishers, 1998].We have started a study in order to compare the power consumption of two Intellectual Property (IP), a counter circuit and an image transform circuit. Both circuits have been implemented using FPGA Family circuits from ALTERA and Hardware Copy of the circuits which are close to the ASIC implementation. A full ASIC implementation using UMC 0.13 μm have be also characterized in terms of power.FPGA power consumption estimation flow is based on ALTERA tools (QuartusII) that provide accurate overall power consumption for a set of input stimuli, on various targets: FPGA families and Hardware Copy. ASIC power consumption estimation flow is based on Synopsys Power tools.     

Rapid Synthesis and Simulation of Computational Circuits in an MPPA

A computational circuit is custom-designed hardware which promises to offer maximum speedup of computationally intensive software algorithms. However, the practical needs to manage development cost and many low-level physical design details erodes much of the potential speedup by distracting attention away from high-level architectural design. Instead, designers need an inexpensive, processor-like platform where computational circuits can be rapidly synthesized and simulated. This enables rapid architectural evolution and mitigates the risk of producing custom hardware. In this paper we present a tool flow (RVETool) for compiling computational circuits into a massively parallel processor array (MPPA). We demonstrate the CAD runtime is on average 70× faster than FPGA tools, with a circuit speed 5.8× slower than FPGA devices. Unlike the fixed logic capacity of FPGAs, RVETool can trade area for simulation performance by targeting a wide range in the number of processor cores. We also demonstrate tool scalability to very large circuits, synthesizing, placing, and routing a ≈1.6 million gate random circuit in 54 min.     

基于ASIC技术的电子防盗系统及其实现

提出了一种将专用集成电路应用于电子防盗系统设计的新方法。介绍了系统组成和工作流程,给出了ＦＰＧＡ验证结果。该系统利用ＡＳＩＣ保密性能好的特点,工作时误报率低。     

FPGA-based digit-serial CSD FIR filter for image signal format conversion

This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs.