A 0.33 V 2.5 μW cross-point data-aware write structure,read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS

Conventional data-aware structure SRAMs consume unnecessary dynamic power during the read phase due to the read-half-select issue. In this paper, a 9T-based read-half-select disturb-free SRAM architecture with the cross-point data-aware write strategy is proposed. Based on the proposed write-half-select and read-half-select disturb-free strategy, our 9T bitcell structure improves the read and write SNM by 2.5X and 2.4X compared to traditional bitcells. Furthermore, the proposed strategy and 9T bitcell structure can reduce the read power dissipation on bitline of the SRAM array by 5.14X compared with traditional SRAMs. Based on the proposed architecture, a 16Kb SRAM is fabricated in a 130 nm CMOS which is fully functional from 1.2 V down to 0.33 V. The minimal energy per cycle is 11.8pJ at 0.35 V. The power consumption at 0.33 V is 2.5 µW with 175 kHz. The proposed SRAM has 1.5X and 4.2X less total power and leakage power than other works.     

Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability

In this work, we proposed a single-ended read disturb-free 9T SRAM cell for bit-interleaving application. A column-aware feedback-cutoff write scheme is employed in the cell to achieve higher write margin and non-intrusive bit-interleaving configuration. And a dynamic read-decoupled assist scheme is utilized by cutting loop to relax the interdependence between stability and read current, resulting in robust read operation and better read performance simultaneously. Moreover, the lower write and leakage energy consumptions are also achieved. We compared area, stability, SNM sensitivity and energy consumption between proposed 9T and standard 6T bit-cells. The write ability of 9T cell is 1.40× higher that of 6T cell at 1.0 V, and 8.16× higher at 0.3 V. The write and leakage energy dissipations are 26% and 13% lower than that of 6T at 1.0 V. In addition, robust read and better process variation tolerance are provided for proposed design with area penalty.     

A compact low-power 4-port register file with grounded write bitlines and single-ended read operations

An area-efficient 4-port register file with low power consumption is presented for mobile application processors. Area efficiency at array level is achieved with a novel compact bitcell that supports single-ended one-sided read operations using the direct read access mechanism and single-ended write operations. A write-assist technique ensures robust operation down to 0.75 V. Single-ended one-sided read operations help maintain sufficient bitcell stability at 0.75 V. Factors that contribute toward low power consumption include grounded write bitlines, bitcells with low leakage currents, individual read clock generators for top and bottom halves of the array, and smaller wordline buffers and capacitance due to a smaller bitcell. For a 2-Kib array implemented in TSMC 65 nm low power (LP) dual-V_t CMOS process, the proposed design achieves 17.8% reduction in silicon area, 19.6% lower active power, and 12.8% lower standby power when compared to the conventional 4-port dual-V_t register file. These benefits are obtained by trading off operating frequency at voltages below the nominal, read and write bitcell noise margins, and data retention voltage.     

A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory

This paper presents a new read and write assist technique to enable lower voltage operation for Static Random Access Memory (SRAM). The ability to scale the operating voltage with frequency of the chip has big impact on power consumption (Pαv²). The lower end of the operating voltage (V_ddmin) for most chips is determined by the stability of the SRAM cell. The new technique uses a contention-free circuit to generate a Reduced Voltage Swing (RVS) on the wordline (VWL) and selectively reduce the supply to the bitcell (V_ddmem) during write. The required VWL and bitcell voltages are programmable and controllable to adapt to performance and yield requirements. An 8 KB memory test-chip was designed to demonstrate this technique in a low-leakage 45 nm process technology. Results show a 7 to 19% improvement in V_ddmin depending on the process corner, which translates into 14–40% reduction on active power. The proposed technique has 4% area overhead and minimal impact to speed.     

Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based technology

We propose a flex-pass-gate SRAM (Flex-PG SRAM), which is a FinFET-based SRAM to enhance both the read and write margins independently. The flip-flop in the Flex-PG SRAM consists of usual FinFETs, while its pass gates consist of double-“independent”-gate FinFETs, i.e., “four-terminal”- (4T-) FinFETs. A 4T-FinFET has a variable threshold voltage controlled by the second gate voltage. This function enables the Flex-PG SRAM to optimize the current drivability in the pass gates according to operational conditions of read and write. This results in enhancement of both the read and write margins. TCAD simulations revealed that the Flex-PG SRAM increases the read margin by 71 mV without the cell size penalty and decrease in the write margin, even when its 6σ tolerance is ensured. Also, a half-cell experiment proved its feasibility.     

A technique to mitigate impact of process,voltage and temperature variations on design metrics of SRAM Cell

This paper presents a technique for designing a variability aware SRAM cell. The architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception that the access pass gates are replaced with full transmission gates. The paper studies the impact of V_t (threshold voltage) variation on most of the design metrics of SRAM cell. The proposed design achieves 1.4× narrower spread in I_READ at the expense 1.2× lower I_READ at nominal V_DD. It offers 1.3× improvements in T_RA (read access time) distribution at the expense of 1.2× penalty in read delay. The proposed bitcell offers 1.1× tighter spread in T_WA (write access time) incurring 1.3× longer write delay. It shows 180 mV of SNM (static noise margin) and is equally stable in hold mode. It offers 1.3× higher RSNM (100 mV) compared to 6T (75 mV). It exhibits improved SINM (static current noise margin) distribution at the expense of 1.6× lower WTI (write trip current). It offers 1.05× narrower spread in standby power. Thus, comparative analysis based on Monte Carlo simulation exhibits that the proposed design is capable of mitigating impact of V_t variation to a large extent.     

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (V_WL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal V_DD. A specific V_WL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a V_WL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65 nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of V_WL with a small impact on read time.     

A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology

A new asymmetric 6T-SRAM cell design is presented for low-voltage low-power operation under process variations. The write margin of the proposed cell is improved by the use of a new write-assist technique. Simulation results in 65 nm technology show that the proposed cell achieves the same RSNM as the asymmetric 5T-SRAM cell and 77% higher RSNM than the standard 6T-SRAM cell while it is able to perform write operation without any write assist at V_DD=1 V. Monte Carlo simulations for an 8 Kb SRAM (256×32) array indicate that the scalability of operating supply voltage of the proposed cell can be improved by 10% and 21% compared to asymmetric 5T- and standard 6T-SRAM cells; 21% and 53% lower leakage power consumption, respectively. The proposed 6T-SRAM cell design achieves 9% and 19% lower cell area overhead compared with asymmetric 5T- and standard 6T-SRAM cells, respectively. Considering the area overhead for the write assist, replica column and the replica column driver of 2.6%, the overall area reduction in die area is 6.3% and 16.3% as compared with array designs with asymmetric 5T- and standard 6T-SRAM cells.     

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body–source voltage dynamically. Proper usage of low-threshold voltage (L-\(V_{\mathrm{t}}\)) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power–delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.     

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the power consumption of the cell. This shaped wordline pulse results in improved read noise margin without any degradation in access time for small wordline load. The improvement is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time (depending on the size of boosting capacitance), wordline voltage becomes negative and charges up to zero after a specific time that results in a lower leakage current compared to conventional SRAM. The proposed technique results in at least 2× improvement in read noise margin while it improves write margin by 3× for lower supply voltages than 0.7 V. The leakage power for the proposed SRAM is reduced by 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The main advantage of the proposed wordline driver is the improvement of dynamic noise margin with less than 2.5% penalty in area. TSMC 65 nm technology models are used for simulations.     

Implementation of low-voltage static RAM with enhanced data stability and circuit speed

This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256 Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18 μm CMOS logic process. For 0.8 V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.     

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

Sub-1V embedded SRAM with bit-error immune dual-boosted cell technique

A sub-1 V operating SRAM based on the dual-boosted cell technique is described. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell readout current. A 0.18 mum 256 kbit SRAM macro has been fabricated with the proposed technique, which demonstrated: 0.8 V operation with 50 MHz while consuming a power of 65 muW/MHz; 400 mV read SNM at 0.8 V power supply; and a reduction by 87% in bit-error rate compared with that of a conventional SRAM     

A low voltage and low power parallel electronically tunable resistor with linear and nonlinear characteristics

In this paper a bilateral resistive circuit is designed and presented with is work as a positive and negative electronically tunable resistor and has zero DC offset. The proposed topology is designed by paralleling two electronically tunable resistors to obtain lower resistive values and decreasing nonlinearity percent. The proposed topology is low voltage and low power and with proper transcurrent circuit, its current–voltage characteristics can be linear, expansive (square) and compressive (square root). Its supply voltages are ±1 V and its dynamic range is ±1 V too. The designed circuit is simulated in an industrial 65 nm CMOS process. The linear version is tunable over the wide resistance range of 7 kΩ–37 GΩ.     

A new type of low power read circuit in EEPROM for UHF RFID

A novel low power read circuit without reference in 1 k-bits electrically erasable and programmable (EEPROM) for UHF RFID is designed and implemented in SMIC 0.18 μm EEPROM process. The read power consumption is optimized using a pre-charge sense amplifier. To improve the performance of the read circuit, a self-detect circuit, a read control logic and a feedback scheme are adopted, combined with a special time sequence. For a power supply voltage of 1 V, an average power consumption of 1.6 μA for the read operation of the EEPROM can be achieved when the read clock frequency is 640 kHz. What is more, with a 110 °C temperature change, the read power consumption variation is as low as 12%. The die size of the EEPROM is 0.15 mm², where the read circuit occupies 0.0125 mm².     

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-T4 write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.     

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02 dB and a minimum NF of 2.37 dB from 0.1 to 2.25 GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP_1dB) are better than –7.8 dBm and –19.2 dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24 mW from 1.8 V DC supply with an active area of 0.03 mm².     

Highly stable,low power FinFET SRAM cells with exploiting dynamic back-gate biasing

In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the pull-down transistors is dynamically biased. Simulations indicate that the first proposed cell offers higher read static noise-margin (SNM), higher write-ability, least static/dynamic power, and a comparable read current compared to the previous IG-6TSRAMs. The second cell is a novel independently-controlled-gate FinFET SRAM cell, which provides a high read stability, the highest write-ability, low static power dissipation and high read current compared to the previously reported independently-controlled-gate FinFET SchmitTrigger based SRAM cells. This cell supportsbit-interleaving property at V_DD = 0.4 V with high read/write yields.     

A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications

In this work, a 9T subthreshold SRAM cell is proposed with the reduced leakage power and improved stability against the PVT variations. The proposed cell employs the read decoupling to improve the read stability, and the partial feedback cutting approach to control the leakage power with improved read/write ability. The incorporated stacking effect further improves the leakage power. The simulated leakage power for the proposed cell is 0.61×, 0.49×, 0.80× and 0.55×, while the read static noise margin (RSNM) is 2.5×, 1×, 1.05× and 0.96×, write static noise margin (WSNM) 0 is 1.5×, 1.8×, 1.68× and 1.9× and WSNM 1 is 0.95×, 1.2×, 1.05×, and 1.2× at 0.4 V when compared with the conventional 6T and state of arts (single ended 6T, PPN based 10T and data aware write assist (DAWA) 12T SRAM architectures) respectively. The minimum supply voltage at which this cell can successfully operate is 220 mV. A 4 Kb memory array has also been simulated using proposed cell and it consumes 0.63×, 0.67× and 0.63× less energy than 6T during read, write 1 and write 0 operations respectively for supply voltage of 0.3 V.