Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition. The battery life is the critical problem for wearable devices. The non-volatile memory (NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption, NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory (DRAM). In this paper, we assume to use hybrid random access memory (RAM) and NVM architecture for the smart bracelet system. This paper presents a data management algorithm named bracelet power-aware data management (BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.     

基于新型非易失存储器的混合内存架构的内存管理机制

随着互联网和云计算技术的迅猛发展,现有动态随机存储器（Dynamic Random Access Memory,DRAM）已无法满足一些实时系统对性能、能耗的需求.新型非易失存储器（Non-Volatile Memory,NVM）的出现为计算机存储体系的发展带来了新的契机.本文针对NVM和DRAM混合内存系统架构,提出一种高效的混合内存页面管理机制.该机制针对内存介质写特性的不同,将具有不同访问特征的数据页保存在合适的内存空间中,以减少系统的迁移操作次数,从而提升系统性能.同时该机制使用一种两路链表使得NVM介质的写操作分布更加均匀,以提升使用寿命.最后,本文在Linux内核中对所提机制进行仿真实验.并与现有内存管理机制进行对比,实验结果证明了所提方法的有效性.     

Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory

Non-volatile memories (NVMs) show great potential in replacing DRAM as the main memory in many embedded systems because of their attractive characteristics such as low cost, high density, and low energy consumption. However, the problem of asymmetric read and write costs has to be addressed before the advantages of NVM can be fully exploited. That is, the cost of write operation is much more expensive than the cost of read operation on NVMs. The existing techniques for loop optimization cannot be used effectively with non-volatile main memory because this special feature is not considered. In this paper, we propose an efficient loop scheduling algorithm, the Rotation with Maximum Bipartite Matching (RMBM) algorithm, to address the problem of expensive write operations on non-volatile main memory for chip multiprocessors (CMPs). It achieves high parallelism for a loop and, at the same time, reduces the number of write operations on NVM. The experimental results show that the RMBM algorithm reduces the number of write activities on NVM by 34.5 % on average compared with the traditional rotation scheduling algorithm. The execution time is reduced by 20.5 %, and the energy consumption is also reduced by 15.03 % on average using the RMBM algorithm. In other words, the average lifetime of NVM can be extended by more than 2 times using the proposed technique.     

Energy-Efficient Streaming Using Non-volatile Memory

The disk and the DRAM in a typical mobile system consume a significant fraction (up to 30%) of the total system energy. To save on storage energy, the DRAM should be small and the disk should be spun down for long periods of time. We show that this can be achieved for predominantly streaming workloads by connecting the disk to the DRAM via a large non-volatile memory (NVM). We refer to this as the NVM-based architecture (NVMBA); the conventional architecture with only a DRAM and a disk is referred to as DRAMBA. The NVM in the NVMBA acts as a traffic reshaper from the disk to the DRAM. The total system costs are balanced, since the cost increase due to adding the NVM is compensated by the decrease in DRAM cost. We analyze the energy saving of NVMBA, with NAND flash memory serving as NVM, relative to DRAMBA with respect to (1) the streaming demand, (2) the disk form factor, (3) the best-effort provision, and (4) the stream location on the disk. We present a worst-case analysis of the reliability of the disk drive and the flash memory, and show that a small flash capacity is sufficient to operate the system over a year at negligible cost. Disk lifetime is superior to flash, so that is of no concern.     

A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

New investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.     

Data Allocation with Minimum Cost under Guaranteed Probability for Multiple Types of Memories

As the advance of memory technologies, multiple types of memories such as different kinds of non-volatile memory (NVM), SRAM, DRAM, etc. provide a flexible configuration considering performance, energy and cost. For improving the performance of systems with multiple types of memories, data allocation is one of the most important tasks. The previous studies on data allocation problem assume the worst (fixed) case of data-access frequencies. However, the data allocation produced by employing worst case usually leads to an inferior performance for most of time. In this paper, we model this problem by probabilities and design efficient algorithms that can give optimal-cost data allocation with a guaranteed probability. We propose DAGP algorithm produces a set of feasible data allocation solutions which generates the minimum access time or cost guaranteed by a given probability. We also propose a polynomial-time algorithm, MCS algorithm, to solve this problem. The experiments show that our technique can significantly reduce the access cost compared with the technique considering worst case scenario. For example, comparing with the optimal result generated by employing the worst cases, DAGP can reduce memory access cost by 9.92 % on average when guaranteed probability is set to be 0.9. Moreover, for 90 percents of cases, memory access time is reduced by 12.47 % on average. Comparing with greedy algorithm, DAGP and MCS can reduce memory access cost by 78.92 % and 44.69 % on average when guaranteed probability is set to be 0.9.     

An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies

Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things (IoT) deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory (DRAM) with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops (NVFFs) seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.     

Phase Change Memory lifetime enhancement via online data swapping

As DRAM technology is facing scalability limitations due to its excessive leakage power in nano-scale technologies, various non-volatile memory technologies have been emerged to replace it in memory hierarchy. Among these technologies, Phase Change Memory (PCM) is a promising technology for main memory due to its near-zero leakage power, higher density, non-volatility and soft error immunity. However, its major drawbacks, including high write energy and limited write endurance, have prevented its usage as a drop-in replacement of DRAM technology. In this paper, we propose a technique to swap data between memory lines with goal of reducing bit flips. The proposed swapping technique finds the best place to write a chunk of data among a limited set of lines to minimize number of bit flips. The proposed swapping operation works online i.e, does not require any data profiling. Moreover, it does not require major modifications of existing solutions and works only by the addition of a proposed circuitry. It is remarkable that, this technique is additive to various other architectures aiming at PCM lifetime enhancement. Experimental results carried out on a quad core CMP system show that the proposed technique prolongs PCM main memory lifetime by 48% which is achieved at the price of 1% and 2% overhead in read and write latencies respectively.     

Memory-fast computer memories

The search for new dynamic RAM (DRAM) technologies to reduce memory access time and so unleash computer performance is discussed. The typical memory hierarchy of internal registers, cache, main memory, and mass storage is described. DRAM technologies that aim at simplifying this hierarchy by speeding up main memory to the point where the need for a separate, external cache is moot are examined     

高k介质在浮栅型非挥发性存储器中的应用

随着微电子技术节点不断向前推进,基于传统浮栅结构的非挥发性存储器(NVM)技术遇到严重的技术难点,其中最主要的问题是SiO2隧穿层已经接近厚度极限,很难继续减薄.作为改进措施,引入高k介质作为新型隧穿层材料.文章介绍了高k材料的研究现状和在NVM器件中应用所取得的进展;最后,对高k介质进一步应用的研究趋势进行了展望.     

Organic small-molecule heterointerface for use in transistor-type non-volatile memory

A chargeable layer is an essential element for charge transfer and trapping in a transistor-based non-volatile memory device. Here we demonstrate that a heterointerface layer comprising of two different small molecules can show electrical memory characteristics. The organic heterointerface layer was fabricated with a pentacene and tris(8-hydroxyquinoline) aluminum (Alq3) layers by sequential vapor deposition without breaking the vacuum state. Pentacene was adopted as the active layer on the top, and Alq3 was used as the bottom layer for charge trapping. The bottom-gate top-contact transistor with an organic heterointerface layer showed distinct non-volatile memory behaviors and showed high air stability and reliability. We investigated the energy structure of the pentacene/Alq3 heterointerface layer to reveal the operation mechanism of the non-volatile memory and suggested that the writing/erasing gate bias-dependent energy barrier originating from the difference between the energy levels of the pentacene and Alq3 layers controls the charge transfer at the heterointerface layer. Our approach suggests a simple way to fabricate heterointerface layers for organic non-volatile memory applications with high air stability and reliability.     

非挥发性记忆体Read Disturb测试方法的研究

DDF是一种高容量的NAND Flash。以DDF产品为例,研究和讨论了它的Read Disturb测试方法。受测试时间的限制,只能选择局部的存储区间进行DDF的Read Disturb测试。这样局部区间的测试结果是否能够代表整个芯片的性能,设计了一套实验,对这个课题进行了研究和讨论。依据非挥发性记忆体产品的特性,主要以阈值电压的分布为参考来评价DDF芯片性能的一致性和性能恶化趋势的一致度。最后的实验结果证明了这种测试方法的正确性和合理性。这种分析方法也可以用于其他非挥发性记忆体产品的其他可靠性测试项目的评估。     

Emerging memory technologies: Trends,challenges, and modeling methods

In this paper we analyze the possibility of creating a universal non-volatile memory in a near future. Unlike DRAM and flash memories a new universal memory should not require electric charge storing, but alternative principles of information storage. For the successful application a new universal memory must also exhibit low operating voltages, low power consumption, high operation speed, long retention time, high endurance, and a simple structure. Several alternative principles of information storage are reviewed. We discuss different memory technologies based on these principles, highlight the most promising candidates for future universal memory, make an overview of the current state-of-the-art of these technologies, and outline future trends and possible challenges by modeling the switching process.     

Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase

Post program/erase (P/E) cycled threshold voltage (Vt) instability is one of the major reliability concerns for nanoscale charge trapping (CT) non-volatile memory (NVM) devices. In this study, anomalous program state Vt instability of fully annealed nanoscale nitride based CT NVM device at steady phase is carefully examined. To the best knowledge of the authors, for the first time, the relationship between the derived apparent activation energy (Eaa) of this anomalous program state Vt instability at steady phase and the P/E cycle count is established. They are found to adhere to the power law decay relationship. Anomalous program state Vt instability at steady phase was found to favor lateral redistribution of trapped charge model instead of vertical charge transport model. Physical interpretations of its underlying physical mechanisms and reliability implications to reliability performance of nanoscale nitride based CT NVM were presented. Plausible technical solutions to mitigate the reliability degradation induced by this anomalous program state Vt instability on nanoscale nitride based CT NVM were proposed.     

Indium-tin-oxide,free, flexible,nonvolatile memory devices based on graphene quantum dots sandwiched between polymethylsilsesquioxane layers

Indium-tin-oxide (ITO) free, nonvolatile memory (NVM) devices based on graphene quantum dots (GQDs) sandwiched between polymethylsilsesquioxane (PMSSQ) layers were fabricated directly on polyethylene terephthalate (PET) substrates by using a solution process technique. Current-voltage (I-V) curves for the silver nanowire/PMSSQ/GQD/PMSSQ/poly(3,4-ethylenethiophene):poly(styrene sulfonate)/PET devices at 300 K showed a current bistability. The ON/OFF ratio of the current bistability for the NVM devices was as large as 1 × 10⁴, and the cycling endurance time of the ON/OFF switching for the NVM devices was above 1 × 10⁴ s. The Schottky emission, Poole-Frenkel emission, trapped-charge limited-current, and space-charge-limited current were dominantly attributed to the conduction mechanisms for the fabricated NVM devices based on the obtained I-V characteristics, and energy band diagrams illustrating the “writing” and the “erasing” processes of the devices.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

耐擦写能力测试评估中的样本数选取方法

介绍了非挥发性记忆体产品在进行耐擦写能力测试评估时如何合理地选取样本数的方法.在集成电路的可靠性测试中,样本数通常被理解为样品数,即芯片的颗数.对样本数进行了新的定义,将样本数定义为"芯片颗数×扇区数".这种定义吻合产品可靠性测试对样本的基本定义,可以适用于所有的集成电路可靠性测试,尤其适用于非挥发性记忆体的耐擦写能力测试评估.为了保证相同的测试信心度,考虑到在耐擦写能力测试中周边电路对耐擦写能力测试结果的影响,依照对样本数新的定义,在进行样本数等值选取计算的时候,引入了一个全新的补偿因子f,并且给出了样本数等值计算的公式.实验结果表明,在引入补偿因子f后,样本数等值计算结果更加可靠.     

Memory technology in the future

This article deals with future memory technologies in the next mobile era. First concern is about whether NAND flash memory and DRAM will succeed to evolve beyond 50 nm technologies. Now, technological needs in both memories play a driving engine in pushing further for scaling of a device dimension. Secondly, entirely different types of non-volatile memories can start to penetrate main memory markets as an alternative of NAND flash memory or DRAM in the not-too-distant future. Along with 3-D access transistors, it is widely accepted that 3-D MIM capacitors with ultra high-K dielectrics and noble electrodes will extend silicon technology down to a technology node between 20 to 30 nm. With charge-trap-flash technology, NAND flash memory will extend its technology node down to 20 - 30 nm. Among the candidates for the next generation, PRAM and FRAM begin to burgeon in mass-production. Beyond a 50 nm technology node, scaling of PRAM could be successful by the development of new material and new cell structure. 3-D ferroelectric-capacitor technology is critical for FRAM to enter a 90 nm technology node and beyond.     

电荷俘获存储器阻挡层研究进展

随着非挥发性存储器(NVM)存储单元的特征尺寸进入20 nm节点,使用单层SiO2作为阻挡层的传统电荷俘获存储器结构性能上逐渐受到限制。基于阻挡层在存储器栅堆栈中的作用与基本要求,首先,指出单层SiO2作为阻挡层存在的主要问题,然后对高介电常数材料作为阻挡层时,其禁带宽度、介电常数、内部的缺陷密度以及退火工艺等方面对存储特性的影响进行了分析,同时对近年来研究较多的阻挡层能带工程进行了详细介绍,如SiO2和Al2O3的复合阻挡层结构、多层高介电常数材料的阻挡层结构等。最后,对目前研究进展中存在的问题以及未来的研究方向和趋势进行了总结和展望。     

Memory-a fast path to one memory

A proprietary scheme for a unified memory system that covers all design aspects to ensure fast display and quick computation is presented. This device replaces extant memory types and their interconnects with unique DRAMs, a high-performance, chip-to-chip interface, and a high speed channel. It delivers a byte of data every 2 ns for a block of information up to 256 bytes long. The features and performance of this DRAM are described