Conductive filament formation at grain boundary locations in polycrystalline HfO2 -based MIM stacks: Computational and physical insight

Resistive switching in high-κ (HK) dielectric based metal-insulator-metal (MIM) devices occurs locally and is accompanied by dynamic changes in the structural and electrical properties of the HK dielectric. In polycrystalline HfO₂ HK dielectric based MIM devices, grain boundaries (GBs) play a significant role in the formation of a percolation path for the resistive switching as the GB regions contain a large number of defects and favor the formation of conductive/low resistive paths. In this work, we present a multi-physics based combined Kinetic Monte Carlo-Finite element model (KMC-FEM) 3D percolation framework to simulate the resistive switching (high resistive state (HRS) to low resistive state (LRS)) process in TiN/HfO₂ (5 nm)/Pt MIM stacks. The KMC-FEM model describes the effect of GBs on the formation of conductive path during the HRS to LRS resistive switching. In addition, this model is used to find the statistical distribution of conductive filament/path formation in amorphous and polycrystalline HfO₂ dielectrics. Conductive atomic force microscopy and transmission electron microscopy observations on the characteristics of the HfO₂ dielectrics at the nanometer scale complement the simulation results. The results clearly show that the HRS to LRS resistive switching occurs preferably at the GB regions in polycrystalline HfO₂ and at random locations in amorphous HfO₂ -based MIM stacks.     

Characterization of interfacial reaction and chemical bonding features of LaOx/HfO2 stack structure formed on thermally-grown SiO2/Si(1 0 0)

A stack structure consisting of ～1.5 nm-thick LaO_x and ～4.0 nm-thick HfO₂ was formed on thermally grown SiO₂ on Si(1 0 0) by MOCVD using dipivaloymethanato precursors, and the influence of N₂ annealing on interfacial reaction for this stack structure was examined by using X-ray photoelectron spectroscopy and Fourier transform infrared attenuated total reflection. We found that compositional mixing between LaO_x and HfO₂ becomes significant from 600 °C upwards and that interfacial reaction between HfLa_yO_z and SiO₂ proceeds consistently at 1000 °C in N₂ ambience.     

Improved manufacturability of ZrO2 MIM capacitors by process stabilizing HfO2 addition

A broad compositional range of the dielectric material Zr_1?xHf_xO₂ was evaluated with respect to its applicability in DRAM storage capacitors. The paper reports on phase composition, crystallization behavior, and electrical properties of the mixed system in planar metal-insulator-metal (MIM) capacitors. Admixture of HfO₂ into ZrO₂ proved to stabilize the deposition process at high temperatures without degrading the dielectric properties of the film. Compared to pure ZrO₂ the 30–40% HfO₂ containing films showed improved scalability (capacitance equivalent thickness 0.73 nm at 8 * 10^?9 A/cm²) as well as improved reliability.     

0.6nm-EOT high-k gate stacks with HfSiOx interfacial layer grown by solid-phase reaction between HfO2 and Si substrate

We have developed a process for forming an ultra-thin HfSiO_x interfacial layer (HfSiO_x-IL) for high-k gate stacks. The HfSiO_x-IL was grown by the solid-phase reaction between HfO₂ and Si-substrate performed by repeating the sequence of ALD HfO₂ deposition and RTA. The HfSiO_x-IL grown by this method enables the formation of very uniform films consisting of a few mono-layers, and the dielectric constant of the HfSiO_x-IL is about 7. The FUSI-NiSi/HfO₂ gate stacks with HfSiO_x-IL have achieved 0.6 nm EOT, a very low gate leakage currents between 1 A/cm² and 5 × 10⁻² A/cm², an excellent subthreshold swing of 66mV/dec, and a high peak mobility of 160 cm²/Vs compared to the reference samples without HfSiO_x-IL. These results indicate that the HfSiO_x-IL has a good quality compared to the SiO₂ interfacial layer grown by oxygen diffusion through HfO₂ films.     

Modeling of direct tunneling current through interfacial oxide and high-K gate stacks

In this paper, we present a computationally efficient model to calculate the direct tunneling current from an inverted p-type (1 0 0) Si substrate through interfacial SiO₂ and high-K gate stacks. This model consists of quantum mechanical calculations for the inversion layer charge density and a modified WKB approximation for the transmission probability. The modeled direct tunneling currents agree well with a self-consistent model and experimental data. For the same effective oxide thickness (EOT) of 2 nm, the direct tunneling current of a HfO₂ high-K dielectric (6.4 nm, K_f=25) overlaying a 1 nm thermal oxide is reduced by four orders of magnitude compared with a pure SiO₂ film at low gate voltages. The effects of interfacial oxide thickness, dielectric constant and barrier height on the direct tunneling current have also been studied as a function of gate voltages.     

Phonon-scattering effects in CNT-FETs with different dimensions and dielectric materials

The impact of acoustic and optical phonon scattering on the performance of CNT-FETs is investigated using a full-quantum transport model within the NEGF formalism. Different gate lengths, dielectric materials and chiralities are considered. It is shown that the use of a high-κ dielectric lowers the off-current dominated by phonon-assisted band-to-band tunneling. The device scalability is demonstrated: with the oxide thickness fixed to 1.5 nm, good performance is obtained with 15 nm and 10 nm gate lengths with SiO₂ and HfO₂ gate dielectrics, respectively. The role of phonon scattering in CNT-FETs of different chiralities is investigated for the HfO₂ devices. A similar analysis has also been carried out for source/drain underlap geometries. The results confirm that the calculation of the off-currents and delay times is strongly influenced by phonon scattering.     

Structural,compositional and electrical characterization of Si-rich SiOx layers suitable for application in light sensors

Metal-Oxide-Silicon (MOS) structures containing silicon nanoparticles (SiNPs) in three different gate dielectrics, single SiO_x layer (c-Si/SiNPs-SiO_x), two-region (c-Si/thermal SiO_x/SiNPs-SiO_x) or three-region (c-Si/thermal SiO₂/SiNPs-SiO_x/SiO₂) oxides, were prepared on n-type (100) c-Si wafers. The silicon nanoparticles were grown by a high temperature furnace annealing of sub-stoichiometric SiO_x films (x=1.15) prepared by thermal vacuum evaporation technique. Annealing in N₂ at 700 or 1000 °C leads to formation of amorphous or crystalline SiNPs in a SiO_x amorphous matrix with x=1.8 or 2.0, respectively. The three-region gate dielectric (thermal SiO₂/SiNPs-SiO₂/SiO₂) was prepared by a two-step annealing of c-Si/thermal SiO₂/SiO_x structures at 1000 °C . The first annealing step was carried out in an oxidizing atmosphere while the second one was performed in N₂. Cross-sectional Transmission Electron Microscopy and X-ray Photoelectron Spectroscopy have proven both the nanoparticle growth and the formation of a three region gate dielectric. Annealed MOS structures with semitransparent aluminum top electrodes were characterized electrically by current/capacitance–voltage measurements in dark and under light illumination. A strong variation of the current at negative gate voltages on the light intensity has been observed in the control and annealed at 700 °C c-Si/SiNPs-SiO_x/Al structures. The obtained results indicate that MOS structures with SiO_1.15 gate dielectric have potential for application in light sensors in the NIR–Visible Light–UV range.     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.     

Dielectric surface-polarity tuning and enhanced operation stability of solution-processed organic field-effect transistors

The electrical performance of triethylsilylethynyl anthradithiophene (TES-ADT) organic field-effect transistors (OFETs) was significantly affected by dielectric surface polarity controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH₃)₂Cl) to 300-nm-thick SiO₂ dielectrics. On the untreated and treated SiO₂ dielectrics, solvent–vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The operation and bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with a decrease in dielectric surface polarity. Among dielectrics with similar capacitances (10.5–11 nF cm⁻²) and surface roughnesses (0.40–0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and a charge-carrier mobility ∼1.32 cm² V⁻¹ s⁻¹, on–off current ratio >10⁶, threshold voltage ∼0 V, and long-term operation stability under negative bias stress.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

Paramagnetic Ge dangling bond type defects at (1 0 0)Si1−xGex/SiO2 interfaces (Invited Paper)

The work addresses the occurrence of Ge dangling bond type point defects at Ge_xSi_1?x/insulator interfaces as evidenced by conventional electron spin resonance (ESR) spectroscopy. Using multifrequency ESR, we report on the observation and characterization of a first nontrigonal Ge dangling bond (DB)-type interface defect in SiO₂/(1 0 0)Ge_xSi_1?x/SiO₂/(1 0 0)Si heterostructures (0.27 ? x ? 0.93) manufactured by the condensation technique, a selective oxidation method enabling Ge enrichment of a buried epitaxial Si-rich SiGe layer. The center, exhibiting monoclinic-I (C_2v) symmetry is observed in highest densities of ～7 × 10¹² cm^?2 of Ge_xSi_1?x/SiO₂ interface for x ～ 0.7, to disappear for x outside the ]0.45–0.87[ interval, with remarkably no copresence of Si P_b-type centers. Neither are trigonal Ge DB centers observed, enabling unequivocal spectral analysis. Initial study of the defect passivation under annealing in molecular H₂ has been carried out. On the basis of all data the defect is depicted as a Ge P_b1-type center, i.e., distinct from a trigonal basic Ge P_b(0)-type center (Ge₃Ge). The modalities of the defect’s occurrence as unique interface mismatch healing defect is discussed, which may widen our understanding of interfacial DB centers in general.     

Application of non-linear optical second harmonic generation and X-ray absorption and spectroscopies to defect related properties of Hf silicate and Hf Si oxynitride gate dielectrics

Three different Hf oxide based dielectrics have emerged as viable candidates for applications in advanced ULSI devices. This article focuses on two of these: (i) phase separated Hf silicates with (i) 70–85% nano-crystalline HfO₂ with a nano-grain size <2 nm, and 15–30% ～2 nm non-crystalline SiO₂ inclusions, and (ii) Hf Si oxynitride alloys, the most promising of which has a composition, (HfO₂)_0.3(SiO₂)_0.3(Si₃N₄)_0.4 designated as 3/3/4 Hf SiON. X-ray absorption spectroscopy has been applied to identification of defect associated with vacancy structures in phase separated silicates, and network disruption defects in the Hf Si oxynitrides. Optical second harmonic generation is introduced in this article for the first time as a non-invasive approach for detecting macroscopic strain, that is shown to be absent in these low defect density dielectrics, the phase separated Hf silicates, and Hf Si oxynitrides, but present in HfO₂ films, and Hf silicates with lower HfO₂ content, e.g., the 40% HfO₂ film of this article.     

Characterization of CoxNiyO hybrid metal oxide nanoparticles as charge trapping nodes in nonvolatile memory devices

The Co_xNi_yO hybrid metal oxide nanoparticles (HMONs) embedded in the HfO_xN_y high-k dielectric as charge trapping nodes of the nonvolatile memory devices have been formed via the chemical vapor deposition using the Co/Ni acetate calcined and reduced in the Ar/NH₃ ambient. A charge trap density of 8.96 × 10¹¹ cm^?2 and a flatband voltage shift of 500 mV were estimated by the appearance of the hysteresis in the capacitance–voltage (C–V) measurements during the ±5 V sweep. Scanning electron microscopy image displays that the Co_xNi_yO HMONs with a diameter of ～10–20 nm and a surface density of ～1 × 10¹⁰ cm^?2 were obtained. The mechanism related to the writing characteristics are mainly resulted from the holes trapping. Compared with those devices with the Co_xNi_yO HMONs formed by the dip-coated technique, memory devices with the Co_xNi_yO HMONs fabricated by the drop-coated technique show improved surface properties between the Co_xNi_yO HMONs and the HfON as well as electrical characteristics.     

Interface studies of ALD-grown metal oxide insulators on Ge and III–V semiconductors (Invited Paper)

Atomic layer deposited (ALD) HfO₂/GeO_xN_y/Ge(1 0 0) and Al₂O₃/In_0.53Ga_0.47As(1 0 0) ? 4 × 2 gate stacks were analyzed both by MOS capacitor electrical characterization and by advanced physical characterization to correlate the presence of electrically-active defects with chemical bonding across the insulator/channel interface. By controlled in situ plasma nitridation of Ge and post-ALD annealing, the capacitance-derived equivalent oxide thickness was reduced to 1.3 nm for 5 nm HfO₂ layers, and mid-gap density of interface states, D_it = 3 × 10¹¹ cm^?2 eV^?1, was obtained. In contrast to the Ge case, where an engineered interface layer greatly improves electrical characteristics, we show that ALD-Al₂O₃ deposited on the In_0.53Ga_0.47As (1 0 0) ? 4 × 2 surface after in situ thermal desorption in the ALD chamber of a protective As cap results in an atomically-abrupt and unpinned interface. By avoiding subcutaneous oxidation of the InGaAs channel during Al₂O₃ deposition, a relatively passive gate oxide/III–V interface is formed.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

Temperature dependence of electrical properties for MOS capacitor with HfO2/SiO2 gate dielectric stack

We investigated the temperature dependence of C–V and I–V characteristics in p-type Metal Oxide Semiconductor (MOS) capacitors with HfO₂/SiO₂ dielectric stacks. Dramatic degradation in the C–V characteristics at/over the measurement temperature of 125 °C was observed, which was caused by the increased effective oxide thickness, oxide trapped charge density, and interfacial density of state (D_it) with rising temperature during bias temperature stress. In the accumulation region, the leakage current density displayed strong temperature dependence in the ?3 V<Vg<0 V region, as expected for the direct tunneling compared to the trap-assisted component (DT+TAT) effect. The conduction mechanism was transformed into Fowler–Nordheim (FN) tunneling (weak T and Vg dependence) from DT+TAT (strong T and Vg dependence) at Vg <?3 V, which was confirmed by FN tunneling fitting. According to the conventional Shockley–Read–Hall model, the different levels in D_it were found at various measurement temperatures to interpret the strong temperature dependence and weak Vg dependence inversion current property.     

Effect of heat treatments on electric dipole at metal/high-k dielectric interfaces measured by in situ XPS

The paper describes the application of X-ray photoelectron spectroscopy (XPS) based method to quantify changes in the electric dipole formed at the metal/dielectric interface following heat treatments of metal–oxide–semiconductor (MOS) stack in different environments. The presented results on Me (Me = Au, Ni)/dielectric (dielectric = HfO₂, LaAlO₃) evidence the oxygen vacancies generated in dielectric contribute to the effective work function changes.     

Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

The use of co-sputtered Zirconium Silicon Oxide (Zr_xSi_1−xO₂) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO₂ and ZrO₂ targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the Zr_xSi_1−xO₂ film up to 600 °C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr_0.85Si_0.15O₂ dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81 mV/dec), field-effect mobility (μ_FE=51.7 cm²/Vs), and threshold voltage shift (ΔV_TH=0.03 V).     

Achieving time-of-flight mobilities for amorphous organic semiconductors in a thin film transistor configuration

We observe bulk-like hole transport in amorphous organic semiconductors in a thin film transistor (TFT) configuration. Five different organic hole transporters (HTs) commonly used in organic light-emitting diodes are investigated. When these HTs are deposited on SiO₂ gate dielectric layer, the TFT mobilities are 1–2 orders of magnitude smaller than those obtained from bulk films (3–8 μm) using time-of-flight (TOF) technique. The reduction of hole mobilities can be attributed to the interactions between the organic HTs and the polar SiO bonds on the gate dielectric layer. Detailed temperature dependence studies, employing the Gaussian disorder model, indicate that the SiO₂ gate dielectric contributes between 60 and 90 meV of energetic disorder in the charge hopping manifold. Besides SiO₂ gate dielectric, similar effects can also be observed for other polar insulators including polymeric PMMA and BCB, or HMDS-modified SiO₂. However, when a common non-polar polymer, polystyrene (PS), is employed as the dielectric layer, the dipolar energetic disorder becomes negligible. Holes effectively experience bulk-like transport on the PS gate dielectric surface. TFT mobilities extracted from all five organic HTs are in excellent agreements with TOF mobilities. The present study should have broad applications in the transport characterization of amorphous organic semiconductors.     

Solution-processed single-crystal perylene diimide transistors with high electron mobility

We have successfully demonstrated a single-crystal field-effect transistors (FETs) based on an asymmetric perylenetetracarboxylic diimide (a-PDI) compound with polystyrene (PS)/SiO₂ bilayer as gate dielectric. The single crystals are in-situ grown on substrate from simple solution evaporation method, thus may be suitable for large area electronics applications. The PS modified gate dielectric could minimize charge trapping by the hydroxyl groups of the SiO₂ surface. The resulting solution processed single crystals transistors are characterized in ambient air, and exhibited maximum electron mobility of ca. 1.2 cm² V⁻¹ s⁻¹ and high I_on:I_off > 10⁵.