Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

基于Pareto支配的MPRM电路面积与可靠性优化

针对MPRM（Mixed-Polarity Reed-Muller）电路的面积与可靠性折中优化问题,在逻辑级建立面积估算模型以及电路SER（Soft Error Rate）解析评价模型,并采用Pareto支配概念对MPRM电路进行面积与可靠性多目标优化.通过对MPRM电路的XOR部分进行树形异或门分解,并考虑多个输出之间异或门的共享,建立面积估算模型.采用信号概率和故障传播方法,并考虑电路中的逻辑屏蔽因素以及信号相关性,建立电路SER解析评价模型.根据所提出的面积和SER评价模型,采用极性向量的格雷码序穷举搜索MPRM的极性空间得到MPRM电路面积与可靠性的Pareto最优解集,并使用效率因子技术指标选取最终解.MCNC基准电路的实验结果表明,与面积最小MPRM电路相比,所选取的MPRM电路可以在较小面积开销的前提下获得较高电路可靠性.     

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits

Recent radiation ground testing campaigns of digital designs have demonstrated that the probability for Single Event Transient (SET) propagation is increasing in advanced technologies. This paper presents a hierarchical reliability-aware synthesis framework to design combinational circuits at gate level with minimal area overhead. This framework starts by estimating the vulnerability of the circuit to SETs. This is done by modeling the SET propagation as a Satisfiability problem by utilizing Satisfiability Modulo Theories (SMTs). An all-solution SMT solver is adapted to estimate the soft error rate due to SETs. Different strategies to mitigate SETs are integrated in the proposed framework to selectively harden vulnerable nodes in the design. Both logical and temporal masking factors of the target circuit are improved to harden sensitive paths or sub-circuits, whose SET propagation probability is relatively high. This process is repeated until the desired soft error rate is achieved or a given area overhead constraint is met. The proposed framework was implemented on different combinational designs. The reliability of a circuit can be improved by 64% with less than 20% area overhead.     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires

We introduce a logic-level soft error mitigation methodology for combinational circuits. The proposed method exploits the existence of logic implications in a design, and is based on selective addition of pertinent functionally redundant wires to the circuit. We demonstrate that the addition of functionally redundant wires reduces the probability that a single-event transient (SET) error will reach a primary output, and, by extension, the soft error rate (SER) of the circuit. We discuss three methods for identifying candidate functionally redundant wires, and we outline the necessary conditions for adding them to the circuit. We then present an algorithm that assesses the SET sensitization probability reduction achieved by candidate functionally redundant wires, and selects an appropriate subset that, when added to the design, minimizes its SER. Experimental results on ISCAS'89 benchmark circuits demonstrate that the proposed soft error mitigation methodology yields a significant SER reduction at the expense of commensurate hardware, power, and delay overhead.     

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.     

Improved single-pass approach for reliability analysis of digital combinational circuits

Designing a highly reliable digital circuit requires tools and techniques for accurately evaluation of its reliability. In this paper, we present an improved single-pass approach for reliability analysis of digital combinational circuits. The main problem of the basic single-pass method is handling reconvergent fan-outs. The proposed method improves the accuracy of the basic single-pass method in two ways. An efficient method is proposed to compute the joint probability between multiple nodes of the circuit which leads to more accurate calculation of correlation coefficients. The second enhancement consists of two methods called case based and mathematical based and concentrates on accurate calculation of conditional joint correlations which makes the algorithm much more dependable than the basic single-pass method. The case based method checks different conditions of the nodes for calculation of conditional joint correlations, while the mathematical based method uses a heuristic expression. The proposed method is applied to a subset of combinational benchmark circuits and our experiments demonstrate that the proposed method eliminates the weaknesses of the basic single-pass method efficiently.     

Reliability enhancement of digital combinational circuits based on evolutionary approach

Reliability has become an integral part of the system design process, especially for those systems with life-critical applications such as aircrafts and spacecraft flight control. The recent rapid growth in demand for highly reliable digital circuits has focused attention on tools and techniques we might use to enhance the reliability of the circuit. In this paper, we present an algorithm to improve the reliability of digital combinational circuits based on evolutionary approach. This method generates a global VHDL file for the selected initial set of components based on inserting multiplexers at the gate inputs of the circuit which helps to perform the simulations in only one session. This simulation framework is combined with single-pass reliability analysis approach to implement the evolutionary algorithm. The search space of the genetic algorithm is limited by the idea of slicing the initial set of components and also circuit partitioning could be used to further overcome the scalability limitations. The framework is applied to a subset of combinational benchmark circuits and our experiments demonstrate that higher reliabilities can be achieved while other factors such as power, speed and area overhead will remain admissible.     

基于保护门的纳米CMOS电路抗单粒子瞬态加固技术研究

随着器件特征尺寸的缩减,单粒子瞬态效应(SET)成为空间辐射环境中先进集成电路可靠性的主要威胁之一。基于保护门,提出了一种抗SET的加固单元。该加固单元不仅可以过滤组合逻辑电路传播的SET脉冲,而且因逻辑门的电气遮掩效应和电气隔离,可对SET脉冲产生衰减作用,进而减弱到达时序电路的SET脉冲。在45 nm工艺节点下,开展了电路的随机SET故障注入仿真分析。结果表明,与其他加固单元相比,所提出的加固单元的功耗时延积(PDP)尽管平均增加了17.42%,但容忍SET的最大脉冲宽度平均提高了113.65%,且时延平均降低了38.24%。     

A practical metric for soft error vulnerability analysis of combinational circuits

Besides the advantages brought by technology scaling, soft errors have emerged as an important reliability challenge for nanoscale combinational circuits. Hence, it is important for vulnerability analysis of digital circuits due to soft errors to take advantage of practical metrics to achieve cost-effective and reliable designs. In this paper, a new metric called Triple Constraint Satisfaction probability (TCS) is proposed to evaluate the soft error vulnerability of combinational circuits. TCS is based on a concept called Probabilistic Vulnerability Window (PVW) which is an inference of the necessary conditions for soft-error occurrence in the circuit. We propose a computation model to calculate the PVW’s for all circuit gate outputs. In order to show the efficiency of the proposed metric, TCS is used in the vulnerability ranking of the circuit gates as the basic step of the vulnerability reduction techniques. The experimental results show that TCS provides a distribution of soft error vulnerability similar to that obtained with fault injections performed with HSPICE or with an event driven simulator while it is more than three orders of magnitude faster. Also, the results show that using the proposed metric in the well-known filter insertion technique achieves up to 19.4%, 34.1%, and 55% in soft error vulnerability reduction of benchmark circuits with the cost of increasing the area overhead by 5%, 10%, and 20%, respectively.     

Efficient algorithms to accurately compute derating factors of digital circuits

Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for cost-efficient reliable design. A major step to accurately estimate a circuit SER is the computation of failure probability, which requires the computation of three derating factors, namely logical, electrical, and timing derating. The unified treatment of these derating factors is crucial to obtain accurate failure probability. Existing SER estimation techniques are either unscalable to large circuits or inaccurate due to lack of unified treatment of all derating factors. In this paper, we present fast and efficient algorithms to estimate SERs of circuit components in the presence of single event transients by unified computation of all derating factors. The proposed algorithms, based on propagation of error probabilities and shape of erroneous waveforms, are scalable to very large circuits. The experimental results and comparisons with Statistical Fault Injections (SFIs) using Monte-Carlo simulations confirm the accuracy (only 2% difference) and speedup (5–6 orders of magnitudes) of the proposed technique.     

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of diode-connected transistors (or diodes) between the outputs of the original and shadow gates. These transistors turn on when the voltages of the two gates deviate during a radiation strike. Our experiments show that at the level of a single gate, our circuit structure has a delay overhead about 1.76% on average, and an area overhead of 277%. At the circuit level, however, we do not need to protect all gates. We present a methodology to selectively protect specific gates of the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demonstrate that at the circuit level, the average delay overhead is about 3% and the average placed-and-routed area overhead is 28%, compared to an unprotected circuit (for delay mapped designs). We also propose an improved circuit protection algorithm to reduce the area overhead associated with our approach. With this approach for circuit protection, the area and delay overheads are further lowered.      

基于时序优先的电路容错混合加固方案

为了有效降低容忍软错误设计的硬件和时序开销,该文提出一种时序优先的电路容错混合加固方案。该方案使用两阶段加固策略,综合运用触发器替换和复制门法。第1阶段,基于时序优先的原则,在电路时序松弛的路径上使用高可靠性时空冗余触发器来加固电路;第2阶段,在时序紧张的路径使用复制门法进行加固。和传统方案相比,该方案既有效屏蔽单粒子瞬态(SET)和单粒子翻转(SEU),又减少了面积开销。ISCAS89电路在45 nm工艺下的实验表明,平均面积开销为36.84%,电路平均软错误率降低99%以上。     

A new approach to power estimation and reduction in CMOS digital circuits

Modelling and optimization of dynamic capacitive power consumption in digital static CMOS circuits, taking into consideration a reason of a gate switching—gate control mode, is discussed in the present paper. The term ‘gate control mode’ means that a number and type of signals applied to input terminals of the gate have an influence on total amount of energy dissipated during a single switching cycle. Moreover, changes of input signals, which keep the gate output in a steady state, can also cause power consumption. Based on this observation, complex reasons of power losses have been considered. In consequence, the authors propose a new model of dynamic power consumption in static CMOS gates. Appropriate parameters’ calculation method for the new model was developed. The gate power model has been extended to logic networks, and consequently a new measure of the circuit activity was proposed. Switching activity, which is commonly used as a traditional measure, characterizes only the number of signal changes at the circuit node, and it is not sufficient for the proposed model. As the power consumption parameters of CMOS are dependent on their control mode, the authors used probability of the node control mode as a new measure of the circuit activity. Based on the proposed model, a procedure of combinational circuit optimization for power dissipation reduction has been developed. The procedure can be included in a design flow, after technology mapping. Results of the power estimation received for some benchmark circuits are much closer to SPICE simulations than values obtained for other methods. So the model proposed in this study improves the estimation accuracy. Additionally, we can save several percent of the consumed energy.     

PIPBQ Effect Aware SER Analysis for Combinational Logic Circuits

Technology scaling results in the propagation-induced pulse broadening and quenching (PIPBQ) effect become more noticeable. In order to effectively evaluate the soft error rate for combinational logic circuits, a soft error rate analysis approach considering the PIPBQ effect is proposed. As different original pulse propagating through logic gate cells, pulse broadening and quenching are measured by HSPICE. After that, electrical effect look-up tables (EELUTs) for logic gate cells are created to evaluate the PIPBQ effect. Sensitized paths are accurately retrieved by the proposed re-convergence aware sensitized path search algorithm. Further, by propagating pulses on these paths to simulate fault injection, the PIPBQ effect on these paths can be quantified by EELUTs. As a result, the soft error rate of circuits can be effectively computed by the proposed technique. Simulation results verify the soft error rate improvement comparing with the PIPBQ-not-aware method.     

A New Design Method for Self-Checking Unidirectional Combinational Circuits

In this paper, a new method for the design of unidirectional combinational circuits is proposed. Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters. Unlike previous methods, it is not necessary to localize all the inverters of the circuit at the primary inputs. The average area over head for the described method of circuit transformation is 16% of the original circuit, which is less than half of the area overhead of other known methods. The transformed circuits are monitored by Berger codes, or by the least significant two bits of a Berger code. All single stuck-at faults are detected by the method proposed.     

A method to assess the robustness of cryptographic circuits at the design stage

This paper proposes the use of an FPGA-based fault injection technique, AMUSE, to study the effect of malicious attacks on cryptographic circuits. Originally, AMUSE was devised to analyze the soft error effects (SEU and SET) in digital circuits. However, many of the fault-based attacks used in cryptanalysis produce faults that can be modeled as bit-flip in memory elements or transient pulses in combinational logic, as in faults due to radiation effects. Experimental results provide information that allows the cryptographic circuit designer to detect the weakest areas in order to implement countermeasures at design stage.     

电荷共享对于CMOS逻辑门单粒子瞬态响应的影响

随着CMOS工艺继续缩小,单粒子瞬态脉冲已经成为航天用数字电路的重要故障来源。同时,相邻晶体管之间的电荷共享也随之增加并导致组合电路中单粒子瞬态脉宽缩短,即脉宽抑制效应。之前的文献提出了PMOS到PMOS的脉宽抑制,而本文提出了三种新的脉宽抑制机理(NMOS到PMOS,PMOS到NMOS和NMOS到NMOS),并且通过90纳米三维工艺混合仿真进行了验证。本文的贡献主要有以下三点：1）除了PMOS到PMOS的情况,90纳米工艺下脉宽抑制在PMOS到NMOS和NMOS到NMOS中同样比较明显;2）脉宽抑制效应总体上与粒子入射能量关系较弱,而与粒子入射角度和版图结构(晶体管间距和N阱接触)关系较强。3）紧凑的版图和级联反向单元可以用来促进组合电路中的单粒子瞬态脉宽抑制效应。     

Seamless Pipelining of DSP Circuits

Pipelining is a popularly used technique to achieve higher frequency of operation of digital signal processing (DSP) applications, by reducing the critical path of circuits. But conventionally critical path is estimated by the discrete component timing model in terms of the times required for the computation of additions and multiplications, where arithmetic circuits are considered as discrete components. Pipeline registers are inserted in between arithmetic circuits to reduce the estimated critical path. In this paper, we show that very often the architecture-level pipelining, based on the discrete component timing model, does not result in significant reduction in critical path, but on the other hand increases the latency and register complexity. In order to derive greater advantage of pipelining, propagation delays of different combinational sections could be evaluated precisely at gate level or at least at the level of one-bit adders, and based on that, the critical path could be reduced by placing the pipeline registers seamlessly across the combinational datapath without restricting them to be placed only in between arithmetic circuits. In this paper, we present adequately precise evaluation of propagation delays across combinational path as a network of arithmetic circuits based on seamless view of signal propagation. Using the precise information of propagation delay of combinational sections, we identify the best possible locations of pipeline registers in order to reduce the critical path up to the desired limit. The proposed seamless pipelining approach is found to achieve the desired acceleration of DSP applications without significant pipeline overhead in terms of latency and register complexity.