半导体腐蚀进程中表面液层热对流信息的红外表征

研究了半导体腐蚀过程中液层的红外热像分布特性。经处理分析,实现了对任意时刻表面液层的热对流信息的红外表征。半导体腐蚀过程中产生的化学反应会有热量的释放或吸收,这会引起液层之间能量的交换,从而导致腐蚀液温度的变化。利用红外热像仪可以实时监测这一特性,也可为深入分析、表征液层热对流奠定基础。实验结果表明,越靠近半导体材料与腐蚀液接触面的位置,液层的温度变化越显著,且以半导体材料为中心,由内而外呈梯度状降低,水平液层间的热对流速率明显大于竖直液层间的速率;提取的红外热像截面图可以清楚地表征水平液层及竖直液层的温度变化特性。该方法对分析任意时刻液层的热对流信息具有重要的价值。     

非梯度折射率型面阵平面微透镜

采用常规的光刻热熔法及灰度掩模技术,结合离子束蚀刻与溅射制作面阵非梯度折射率型平面折射和平面衍射微透镜,定性分析了不同的工艺条件下所得到的平面端面微光学折种和形貌特征。给出了在石英衬底表面通过光刻热熔工艺和氩离子束蚀刻所得到的两种球面及圆弧轮廓特征的面阵册形掩模的表面探针测试曲线,对平面微透镜阵列与IRCCD成像芯片和半导体激光器阵列的集成结构作了初步分析。     

Photoelastic stress evaluation and defect monitoring in 300-mm-wafer manufacturing

Process monitoring and tool characterization on product wafers require rapid non-contact and non-destructive evaluation methods. Because all process steps are more or less related to stress in the crystal, the photoelastic stress evaluation by infrared polarimetry is a suitable method for process screening both in wafer and IC manufacturing. It is shown that the full wafer imaging by scanning infrared depolarization can be applied to different steps of wafer manufacturing. After a short introduction into the method and technical realization of on-line photoelastic measurements, the concept of defect-related stress monitoring and process screening is demonstrated for slicing, grinding, lapping, etching, polishing and thermal treatment.     

Experimental study of the process dependence of Mo, Cr, Ti, and W silicon Schottky diodes and contact resistance

This paper reports on the process dependence and electrical characterization of Schottky diodes and ohmic contacts fabricated on p- and n-type silicon wafers. Four metals are systematically studied using identical test structures and characterization methods: Mo, Ti, W, and Cr. The choice of these metals is motivated by their midgap barriers and compatibility with an integrated circuit technology. For these, a thorough investigation of the variation in Schottky-barrier height and contact resistance is carried out for the following process parameters: 1) predeposition wafer preparation, 2) deposition method (sputtering and e-beam evaporation), 3) deposition temperature for the sputtered samples, and 4) annealing. It is found that RF etching previous to metal deposition increases the contact resistance and the barrier height for diodes on p-type silicon. This is of great importance, since RF etching is a very common in situ cleaning process in microelectronic and microelectromechanical systems technologies. Annealing can be used to restore the values of barrier height and contact resistance on wafers exposed to the RF etching.     

Si材刻蚀速率的工艺研究

在采用混合集成方法制造红外热成像阵列器件中,Si的快速刻蚀去除是一个至关重要的问题,它的刻蚀去除质量直接影响红外热成像器件的性能.介绍了等离子体刻蚀的原理、实验过程和实验方法,通过大量工艺实验和测试详细研究和分析了不同刻蚀气体、射频功率和气体流量等工艺参数对Si刻蚀结果的影响,包括刻蚀速率、刻蚀轮廓垂直度和刻蚀表面粗糙度等.通过研究,获得了Si材刻蚀效果与各种工艺参数之间的变化关系,得到了快速刻蚀Si材的较好的工艺参数.     

CMOS-compatible organic light-emitting diodes

We report a new method for the integration of light-emitting devices on a silicon substrate. As an active layer, we use unsubstituted PPV or PPV-based organic macromolecules with a p⁺-silicon anode and a cathode made from aluminum or titanium. The polymer is deposited by spin-coating the precursor, followed by a thermal conversion step to form the macromolecules. All process steps, including the possibility of dry etching of the active layer and the upper electrode, are typical for MOS technology. Spectrum analysis, current-voltage, and intensity measurements have been carried out for device characterization. These organic light-emitting diodes allow the monolithic integration of microelectronic circuits and light-emitting devices on one silicon chip applying only typical MOS process steps     

Recovery of Dry Etching–Induced Damage in <Emphasis Type="Italic">n</Emphasis>-GaN by Nitrogen Plasma Treatment at Growth Temperature

The n-GaN films grown by metal-organic chemical vapor deposition (MOCVD) are etched in an inductively coupled plasma (ICP) reactor chamber. Atomic-force microscopy (AFM) characterization shows an increase of the surface roughness after the etching. Furthermore, Hall measurement and photoluminescence (PL) spectra highlight deterioration of the electrical and optical properties, respectively. Attempts to recover the damage are carried out by nitrogen plasma treatments accompanied by thermal annealing at the growth temperature in a molecular-beam epitaxy (MBE) chamber. Improved electrical and optical properties compared with those of the as-etched GaN, evidenced in both Hall and PL measurements, show a pronounced decrease of the damage introduced by the ICP etching.     

Pattern Based Prediction for Plasma Etch

Plasma etching is a key process for pattern formation in integrated circuit (IC) manufacturing. Unfortunately, pattern-dependent nonuniformities arise in plasma etching processes due to localized microloading and feature size or aspect ratio-dependent reactive ion etch lag. We propose a semi-empirical methodology for characterization and chip-scale modeling of pattern-dependent effects in plasma etching of ICs. We apply this methodology to the study of interconnect trench etching and show that an integrated model is able to predict both pattern density and feature size dependent nonuniformities in trench depth     

偏振不灵敏硅基二氧化硅阵列波导光栅设计

以深刻蚀和热氧化工艺为基础,提出了一种新的阵列波导光栅(AWG)制备技术.这一工艺可使AWG中的波导侧向留有一硅层.采用有限元法和有限差分束传播法分别计算了存在这一硅层时的波导应力分布和有效折射率.结果表明由于这一侧向硅层的存在,使AWG中波导在水平和垂直方向的应力趋于一致,AWG的偏振相关波长明显减小.     

Plasma impedance monitoring for real time endpoint detection of bulk materials etched in ICP tool

Plasma impedance monitoring (PIM) based on electrical measurements is successfully used as an alternative to determine real time detection endpoint during plasma etching of structured bulk materials. In this paper we present the results with this technique for the endpoint detection during the etching of various materials.The endpoint conditions are tested in the sixth harmonic components of the electrical plasma parameters with an RF sensor. The endpoint is determined when an electrical parameter transition is observed. This transition corresponds to the change of the total reactor impedance, and allows the etching of the doped layer to stop on the bulk substrate.Using a Smith chart we determine the best harmonics/electrical monitoring couple parameters for processes on various materials. Resistivity measurements are used before and after etching in order to confirm the usefulness of the PIM method.In this paper, we also demonstrate how to monitor a real time control of non-uniformity during the reactive ion etching (RIE) process in the case of gallium arsenide etching.     

A 90-GHz double-drift IMPATT diode made with Si MBE

For the first time silicon double-drift IMPATT structures have been grown completely by Si molecular-beam epitaxy. The n-type layers are grown at 750 °C on low-resistivity n⁺-type substrates followed by p-type layers at 650 °C. The highly doped p⁺-layers are grown by solid-phase epitaxy in the MBE system. Device design is made for CW operation in W-band. The material is investigated by inspection of beveled samples, defect etching, TEM, SIMS, and spreading resistance measurements. Double-drift flat-profile diodes are housed and mounted employing a technological procedure approved for single-drift diodes. For initial device characterization, dc measurements are performed. Information about doping profile, series, and thermal resistances is obtained. Preliminary RF measurements delivered a maximum output power of 600 mW at 94 GHz with 6.7-percent efficiency from an unoptimized structure.     

Enhanced thermal characterization method of microscale heatsink structures

In the frame of thermal management of electronic devices, finding efficient cooling solutions for next generation equipment is an emerging topic. If a new or improved solution is presented it always requires efficient characterization methods to prove the benefits compared to its predecessor. In case of microscale heatsink structures which are integral parts of modern chip or package level cooling concepts, an efficient measurement method is needed to analyse the performance of structures with different layouts and/or manufacturing technologies. This paper presents an enhanced thermal characterization method of microchannel based cooling structures, determining relevant partial thermal resistances from structure functions obtained by thermal transient testing. Our prior microscale heatsink characterization method was recently improved, accounting e.g. for possible non-idealities of the heat transfer processes. This paper presents how we have improved our measurements setup in detail to deal with these phenomena compared to the previous setup.     

HF蚀刻+逐层抛光法表征熔石英亚表面损伤层深度

脆性材料的研磨过程会不可避免地产生亚表面损伤层,对亚表面损伤层的表征和抑制一直是获得高激光损伤阈值熔石英光学元件的关注热点。回顾了几种亚表面有损表征技术,通过实验重新评价了蚀刻表面峰谷(PV)粗糙度法的可行性,分析了其误差较大的原因。在此基础上,提出了一种新的亚表面损伤层深度检测方法——HF蚀刻+逐层抛光法。分别采用这两种表征技术以及粗糙度估计法、磁流变斜面抛光法对不同工艺研磨的熔石英亚表面裂纹深度进行了对比检测,结果表明这几种表征方法相互符合很好。     

Thermal Conductivity Measurement Methods for SiGe Thermoelectric Materials

A new technique to measure the thermal conductivity of thermoelectric materials at the microscale has been developed. The structure allows the electrical conductivity, thermal conductivity, and Seebeck coefficient to be measured on a single device. The thermal conductivity is particularly difficult to measure since it requires precise estimation of the heat flux injected into the material. The new technique is based on a differential method where the parasitic contributions of the supporting beams of a Hall bar are removed. The thermal measurements with integrated platinum thermometers on the device are cross-checked using thermal atomic force microscopy and validated by finite-element analysis simulations.     

Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy.     

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. In recent CMOS technologies, side-wall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified side-wall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled side-wall spacer formation was developed for fabrication.     

Multiple heat path dynamic thermal compact modeling for silicone encapsulated LEDs

A new multiple heat path dynamic compact model extraction method for LED packages with silicone domes is proposed. The method enables separate characterization of the LEDs dome and the main heat path. It is based on thermal transient analysis of LED configurations with and without the dome. The heat paths de-embedding procedure proposed significantly increases accuracy of the LED thermal characterization compared to a typical singular heat path approach.The method is demonstrated with a representative mid-power LED. The results are validated with steady-state FEA. Suppressed estimation errors of the heat path evaluation are indicated.     

Fabrication and characterization of microscale heat sinks

In the field of thermal management, engineers are well aware of the challenges posed by the increasing level of dissipation. Among the many possible solutions to counter the threat of overheating, one is dealing with the usage of microscale heat sinks, where the forced air or liquid cooling solution is integrated into the electronic package itself. As the System-on-Package integration is not a straightforward task, many fabrication steps have to be fully developed before a successful chip-level cooling system is ready to be used. In this paper, as one of these many steps, we present a refined manufacturing technology which offers the possibility to create the microscale heatsink integrated together with the electronic devices. With the refined manufacturing technology, several channel patterns can be created relatively easily. Nevertheless, only simple channel patterns with integrated diodes are presented now which are tested with an enhanced thermal characterization method developed for microchannel based cooling structures in the last years.     

MEMS器件牺牲层腐蚀释放技术研究

以非制冷红外焦平面阵列和热剪切应力传感器为代表,分析了这两种典型的薄膜悬浮结构和带空腔结构的MEMS器件在进行二氧化硅牺牲层的腐蚀和最终结构释放过程中的各种问题。根据二氧化硅的腐蚀机理,指导了对腐蚀孔(槽)的设计,通过测量不同条件下的腐蚀速度,得出升温、超声、适时更换腐蚀液是加快腐蚀速度的方法,基于粘连现象中拉起长度的概念,提出基于硅衬底下突点制作及释放牺牲层的方法,并获得了成功释放。