Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

GaN-based HEMTs tested under high temperature storage test

In this work, the impact of 1000 h thermal storage test at 325 °C on the performance of gallium nitride high electron mobility transistors grown on Si substrates (GaN-on-Si HEMTs) is investigated. The extensive DC- and pulse-characterization performed before, during and after the stress did not reveal degradation on the channel conduction properties as well as formation of additional trapping states. The failure investigation has shown that only the gate and drain leakage currents were strongly affected by the high temperature storage test. The physical failure analysis revealed a Au inter-diffusion phenomenon with Ni at the gate level, resulting in a worsening of the gate–AlGaN interface. It is speculated that this phenomenon is at the origin of the gate and drain leakage current increasing.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

N2O treatment enhancement-mode InAlN/GaN HEMTs with HfZrO2 High-k insulator

A normally-off InAlN/GaN MIS-HEMT with HfZrO₂ gate insulator was realized and investigated. By using N₂O plasma treatment beneath the gate region, 13 nm InAlN Schottky layer was oxidized to AlON_x + 4 nm InAlN Schottky layer. The strong polarization induced carriers in traditional InAlN/GaN 2 DEG quantum well was reduced for enhancement-mode operation. High-k thin film HfZrO₂ was used for gate insulator of E-mode device to further suppress gate leakage current and enhance device gate operation range. The maximum drain current of E-mode InAlN/GaN MIS-HEMT was 498 mA/mm and this value was higher than previous published InAlN/GaN E-mode devices. The measurement results of low-frequency noise also concluded that the low frequency noise is attributed to the mobility fluctuation of the channel and N₂O plasma treatment did not increase fluctuation center of gate electrode.     

Light-emitting field-effect transistors with π-conjugated liquid crystalline polymer driven by AC-gate voltages

Light-emitting field-effect transistors with a liquid crystalline polymer of poly[(9,9-dioctylfluorenyl-2,7-diyl)-co-bithiophene] (F8T2) were investigated under alternating current (AC) gate operations. Bottom-contact/top-gate devices were fabricated with indium-tin-oxide (ITO) source/drain electrodes, a poly(methyl methacrylate) dielectric and a gold gate electrode. The crystalline F8T2 film exhibited ambipolar characteristics with electron and hole mobilities of 1.8 × 10^?3 and 2.5 × 10^?3 cm²/V s, respectively, although the threshold voltage was considerably higher for electron injection. By applying square-wave voltages to the gate, light emission was obtained at the both edges of the source and drain electrodes by alternating injection of opposite carriers even when the source and drain were grounded. The light intensity was enhanced in the channel region by biasing the source negative while biasing the drain positive where the holes injected from the drain were transported to recombine with the electrons injected at the source edge.     

Study of the leakage current suppression for hybrid-Schottky/ohmic drain AlGaN/GaN HEMT

The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450 V (with no Schottky drain metal) to 855 V with a total drift region length of 9 μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices.     

Gate leakage current suppression and reliability improvement for ultra-low EOT Ge MOS devices by suitable HfAlO/HfON thickness and sintering temperature

Ultra-low effective oxide thickness (EOT) Ge MOS devices with different HfAlO/HfON stacks and sintering temperatures are investigated in this work. The suppression of gate leakage current and improvement of reliability properties can be achieved by either stacked gate dielectrics or a low sintering temperature. Especially, the qualities of the interface and high-k gate dielectric in Ge devices are significantly improved through a low sintering temperature. A 0.5 nm HfAlO/2.5 nm HfON gate stack and a sintering temperature at 350 °C are the suitable conditions to achieve low EOT, gate leakage, and good reliability for Ge MOS devices.     

To observe bidirectional negative differential resistance at room temperature by narrowing transport channels for charge carriers in vertical organic light-emitting transistor

Bidirectional negative differential resistance (NDR) at room temperature with high peak-to-valley current ratio (PVCR) of ～10 are observed from vertical organic light-emitting transistor indium-tin oxide (ITO)/N,N′-di(naphthalene-1-yl)-N,N′-diphenyl-benzidine) (α-NPD)(60 nm)/Al(30 nm)/α-NPD(60 nm)/tris-(8-hydroxyquinoline) aluminium (Alq₃)(50 nm)/Al by narrowing the transport channels for charge carriers with a thick-enough middle Al gate electrode layer to block charge carriers transporting from source electrode to drain electrode. When the transport channel for charge carriers gets large enough, the controllability of gate bias on the drain–source current gets weaker and the device almost works as an organic light-emitting diode only. Therefore, it provides a very simple way to produce NDR device with dominant bidirectional NDR and high PVCR (～10) at room temperature by narrowing transport channels for charge carriers in optoelectronics.     

Polymeric gate dielectric interlayer of cross-linkable poly(styrene-r-methylmethacrylate) copolymer for ferroelectric PVDF-TrFE field effect transistor memory

A new polymeric gate dielectric interlayer of a cross-linkable poly(styrene-random-methylmethacrylate) copolymer is introduced with a good thermal and chemical resistance in bottom gate Ferroelectric Field Effect Transistor (FeFET) memory with pentacene active layer and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) one. A thin uniform PVDF-TrFE film was successfully formed with well defined ferroelectric microdomains on an interlayer. Thickness of the interlayer turns out to be one of the most important factors for controlling gate leakage current which is supposed to be minimized for high ON/OFF bistability of a FeFET memory. An interlayer inserted between gate electrode and PVDF-TrFE layer significantly reduces gate leakage current, leading to source–drain OFF current of approximately 10^?11 A in particular when its thickness becomes greater than approximately 25 nm. A reliable FeFET device shows a clockwise I-V hysteresis with drain current bistablility of 10³ at ±40 V gate voltage.     

Constant current stress of lightly Al-doped Ta2O5

The response of lightly Al-doped Ta₂O₅ stacked films (6 nm) to constant current stress (CCS) under gate injection (current stress in the range of 1 to 30 mA/cm² and stressing time of 50–400 s) has been investigated. The stress creates positive oxide charge, which is assigned to oxygen vacancies but it does not affect the dielectric constant of the films. The most sensitive parameter to the stress is the leakage current. Different degradation mechanisms control the stress-induced leakage current (SILC) in dependence on both the stress conditions and the applied measurement voltage. The origin of SILC is not the same as that in pure and Ti- or Hf-containing Ta₂O₅. The well known charge trapping in pre-existing traps operates only at low level stress resulting in small SILC at accumulation. The new trap generation plays a key role in the SILC degradation and is the dominant mechanism controlling the SILC in lightly Al-doped Ta₂O₅ layers.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Analog switch device using a MOS structure

The development and performance of an analog switch device is presented. The device is based in a metal–oxide–semiconductor (MOS) structure to control the current flow between two terminals, called drain and source. This current is controlled modulating the space charge region width of the MOS structure. Applying a gate voltage the SCR width is increased to a value larger than the theoretical one, this is due to the leakage current existence through the oxide. This oxide characteristic was obtained depositing the film by Atmospheric Pressure Chemical Vapor Deposition (APCVD) at 125 °C. The theoretical and experimental results are presented.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Identification of an RF degradation mechanism in GaN based HEMTs triggered by midgap traps

Quantitative defect spectroscopy was performed on low gate leakage operational S-band GaN HEMTs before and after RF accelerated life testing (ALT) to investigate and quantify potential connections between the evolution of observed traps and RF output power loss in these HEMTs after stressing. Constant drain current deep level transient spectroscopy and deep level optical spectroscopy (CI_D-DLTS and CI_D-DLOS, respectively) were used to interrogate thermally-emitting traps (CI_D-DLTS) and deeper optically-stimulated traps (CI_D-DLOS) so that the entire bandgap can be probed systematically before and after ALT. Using drain-controlled CI_D-DLTS/DLOS, with which traps in the drain access region are resolved, it is found that an increase in the concentration of a broad range of deep states between E_C–1.6 to 3.0 eV, detected by CI_D-DLOS, causes a persistent increase in on-resistance of ~ 0.22 Ω-mm, which is a likely source for the 1.2 dB reduction in RF output power that was observed after stressing. In contrast, the combined effect of the upper bandgap states at E_C–0.57 and E_C–0.72 eV, observed by CI_D-DLTS, is responsible for only ~ 10% of the on-resistance increase. These results demonstrate the importance of discriminating between traps throughout the entire bandgap with regard to the relative roles of individual traps on degradation of GaN HEMTs after ALT.     

On the origin of dynamic Ron in commercial GaN-on-Si HEMTs

There are huge differences in dynamic on-resistance R_on, also known as current-collapse, between current GaN power HEMT technologies. Here we illustrate this fact with dynamic R_on measurements on two commercially available devices from 2 different manufacturers, with one showing more than a factor of 2 increase in dynamic R_on after OFF-state drain bias (type 1) and the other one < 15% change. HTRB stress for 1000 h and 3000 h on type 1 and type 2 respectively was found to only make subtle changes to dynamic R_on, with type 1 still showing a much larger dynamic R_on than type 2. A model for dynamic R_on is presented based on a floating, highly resistive, epitaxial buffer whose potential is determined by parasitic leakage paths. The difficulty in controlling local leakage paths can explain the problems that manufacturers are still finding in suppressing dynamic R_on.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Comprehensive effects of strained Ge1−xSnx and device layout arrangement on a nano-scale Ge-based PMOSFET with a short channel

Layout patterns, including salient gate width and dummy active diffusion region (dummy OD), significantly influence the carrier mobility gain of nano scale devices. Germanium (Ge)-based devices with Ge–tin (GeSn) alloy embedded in the source/drain (S/D) regions have been regarded a promising candidate for higher channel mobility. Second-order piezoresistance coefficients were used to estimate the carrier mobility gain within the desired Ge-based device channel. A 20 nm Ge-based p-type metal oxide semiconductor field effect transistor with 100 nm gate width and 100 nm dummy OD width was selected to explore the layout effect of the short channel device. The device consisted of S/D region Ge_1−xSn_x alloy, compressive-stressed contact etch stop layer, and deposited shallow trench isolation with different process-induced stress magnitudes. Maximum carrier mobility gain of 93.65% was obtained when a 10 nm narrow distance between OD and dummy OD was achieved.     

Effect of contact-etch-stop-layer and Si1-xGex channel mechanical properties on nano-scaled short channel NMOSFETs with dummy gate arrays

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si_0.75Ge_0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.     

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28 nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds = −0.1 V and gate channel length L = 1 μm), and seems to be dominated by a minimally required critical length (L = 0.2 μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.