Study of process induced variability of germanium-pTFET in analog and RF domain

Germanium (Ge) tunnel field effect transistor (TFET) is considered to be an excellent solution to resolve the low on-currents issue of Silicon-based TFETs. Whereas, process variability in any low technology node devices (sub-100 nm) is a crucial subject of matter which affects the device reliability and dependability in advanced SoC applications. In this brief, we have investigated the two main process induced variability a) the thickness of the germanium body b) the thickness of gate oxide in Ge-pTFET using Sentaurus TCAD device simulation. The analysis is performed in complete analog domain along with the study of intrinsic RF performance parameters using small signal equivalent model with non-quasi static effect of the device under consideration. The process induced variability is estimated on the figure of merits (FOMs) such as drain current (I_ds), transconductance (g_m), output resistance (R_o), intrinsic gain (g_mR_o), unity-gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX), transport delay (τ_m), intrinsic resistance (R_gd) and intrinsic capacitances (C_gs, C_gd).     

Impact of the lateral straggle on the Analog and RF performance of TFET

In this work, the effect of the variation in lateral straggle on TFETs performance is demonstrated. The ion implantation technique during fabrication process causes the extension of dopants from source/drain region towards the channel. Even though the use of non-zero tilt angle at the time of ion implantation is necessary to avoid the channeling effect, however, series resistance, threshold voltage roll offs, switching speed and effective channel length of the device get affected by the non abrupt doping profile at the source/drain-body junction. It is established earlier that TFET is very convenient for Analog/RF application owing to its below 60 mV/decade subthreshold swing and reduced short channel effects. In order to show the effect of lateral straggle on TFET’s performance, various Analog figure of merits (FOMs) such as drain current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o), intrinsic gain (g_mR_o) and RF figure of merits (FOMs) like unity gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX) are investigated for the variation in straggle parameter from 0 nm to 5 nm in order to optimize the device performance. The circuit performance of the device for different lateral straggle is carried out using common source amplifier.     

Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation

This paper investigates and compares the impacts of metal-gate work-function variation on important analog figures-of-merit (FOMs) for TFET and FinFET devices using 3-D atomistic TCAD simulations. Our study indicates that, at 0.6 V supply voltage and 0.2 V gate-voltage overdrive, TFET exhibits superior variation immunity regarding transconductance to drain–current ratio (g_m/I_DS), output resistance (R_out) and intrinsic gain, and comparable variability in g_m and cutoff frequency (f_T) as compared with the FinFET counterparts. In addition, how the correlations between pertinent parameters (e.g., g_m and R_out) impact the variation immunity of important analog FOMs are analyzed. Our study may provide insights for low-voltage analog design using TFET/FinFET technologies.     

Superjunction LDMOS on thick-SOI technology for RF applications

The feasibility of applying the superjunction (SJ) concept to a thick-SOI LDMOS transistor for RF base station applications is studied in this paper. The electrical performances of SJ thick-SOI LDMOS transistors are compared with those of the conventional RF LDMOS counterparts through an extensive 3D simulation work in terms of transconductance (g_m), specific-on resistance (R_ON), voltage capability (V_BR) and C-V characteristics. It is expected that SJ thick-SOI LDMOS structures will exhibit a significant R_ON reduction thanks to the N-doping concentration increment in the drift region. The charge balance in structures integrated on thick-SOI substrates with a P-type epitaxial layer requires a fit of the N and P pillar doping concentration, being the P pillar slightly lower doped than the N one. Variation of pillars doping concentrations is directly related to the device performance. Therefore, the R_ON/V_BR trade-off and the R_ON components and the C_gd evolution are shown as a function of pillar doping ratio.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Coupled transmission line analysis for harmonic generation in travelling-wave MESFETs

A coupled transmission line analysis for non-linear MESFETs is presented. It includes the important non-linearities of MESFETs such as input capacitance (C_gs), transconductance (g_m) and output drain conductance (G_gs). The non-linear differential equation for the drain and gate modes can be solved for a relatively weak coupling approximation using the weierstrassian elliptical function.     

Immunity against temperature variability and bias point invariability in double gate tunnel field effect transistor

The weak dependence of the Tunnel Field Effect Transistor (TFET) device characteristics on temperature provides an edge over the conventional MOSFETs in terms of its reliable operation over a wide temperature range applications. This study focusses on the analog/RF performance comparison of DG-TFET and DG-MOSFET, and the impact of temperature variations on some of the key parameters like VIP₃ and intrinsic device gain (g_m * R_out) and the variation of the optimum bias point. In the study of linearity and analog performance, g_m3 (third order derivative of I_ds ? V_gs), VIP₃ in conjunction with intrinsic gain are considered to select the optimum bias point to achieve high gain and better linearity performance. The impact of temperature variations on the ambipolar behavior of a TFET has also been studied.     

Influence of temperature and drain current on source and drain resistances in AlGaN/GaN HEMTs

The behavior of source and drain resistances (R_S and R_D) has been studied for a wide range of drain currents at ambient temperatures from 150 to 500 K. Both parasitic resistances show an important increase as temperature rises, directly related to the reduction in the electron mobility. High drain currents also produce a non-linear increment of R_S and R_D, once the space-charge limited current is exceeded. Both temperature and drain current mechanisms have been modeled together by means of a simple equation, and a good agreement between simulations and measurements is found. Non-linear R_S and R_D allow a more accurate extraction of the intrinsic parameters, especially in the high drain current range. The use of variable parasitic resistances instead of their usually assumed constant values reveals higher intrinsic transconductance (g_m,int) and C_gs.     

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (V_gs) and the transconductance generation factor (g_m/I_d) considering the influence of drain current (I_d) and the transconductance (g_m). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

RF/analog and linearity performance analysis of SiGe source ETLTFET with emphasis on temperature

This study comprises a simulated assessment of the influence of temperature on transfer characteristics of SiGe source-based Epitaxial layer tunnel field effect transistor (SiGe source ETLTFET). Using the transfer characteristics, the temperature dependence of the RF/analog parameters: transconductance (g_m), intrinsic capacitances, cut-off frequency (f_T), transconductance generation factor (TGF), transconductance frequency product (TFP), transit time (τ) and minimum noise figure (NF_min) are also presented. Finally, the linearity metrics including higher-order transconductance (g_m2 and g_m3), input intercept point (IIP₃), voltage intercept point (VIP₃), intermodulation distortion (IMD₃), and 1-dB compression point was evaluated for a wide range of temperature. The findings revealed a substantial impact of temperature on the RF/analog and linearity characteristics. As the temperature rises from 250 to 350 K, the RF/analog characteristics improved, but the linearity figure of merits deteriorates. Moreover, a degraded noise performance (NF_min increases) of the device at elevated temperature was also witnessed.

     

Comprehensive separate extraction of parasitic resistances in MOSFETs considering the gate bias-dependence and the asymmetric overlap length

Parasitic resistances cause degradation of transconductance (g_m), cutoff frequency (f_T), current driving capability, and long term reliability of MOSFETs. We report a comprehensive extraction of parasitic resistance components in MOSFETs for the contact, the spreading current path, and the lightly doped drain region caused by the process, structure, and degradation. We considered the gate bias (V_GS)-dependence and the asymmetric overlap length (L_ov,SD) in the source and drain. We report systematically integrated extraction technique combined with the channel resistance method, the transfer length method, the dual-sweep combinational transconductance technique, the open drain method, and the parasitic junction current method. V_GS-independent resistances were separated to be R_Se = 6.8–6.9 Ω, R_De = 7.4–7.5 Ω, R_SUB = 7.4–7.6 Ω, R_So = 1.8–2.1 Ω, and R_Do = 3.2–3.5 Ω for MOSFETs with and at W/L = 50 μm/0.27 μm. V_GS-dependent intrinsic resistances are obtained to be R_Si = 1.9–4.4 Ω, R_Di = 1.4–3.2 Ω for the same devices. The V_GS-dependent intrinsic channel resistance (R_CH) is extracted with different channel lengths for MOSFETs with L = 0.18 μm/0.27 μm/0.36 μm.     

Electrical parameters degradation of power RF LDMOS device after accelerated ageing tests

This paper reports novel methods for accelerated ageing tests, with comparative reliability between them for stresses applied on power RF LDMOS: Thermal Shock Tests (TST), Thermal Cycling Tests (TCT), High Voltage Drain (HVD) and coupling thermal and electrical effects under various conditions. The investigation findings obtained after various ageing tests show the degradation and the device’s performance shifts for most important electric parameters such as transconductance (Gm), on-state resistance (R_{ds_on}), feedback capacitance (C_rss) and gatedrain capacitance (C_gd). This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. However, this is explained by excitation and trapping of electrons in the oxide-silicon interface at the drain side. A physical simulation software (2D, Silvaco-Atlas) has been used to locate and confirm degradation phenomena.     

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson׳s equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (g_m), output conductance (g_d), early voltage (V_EA), intrinsic gain (A_V), trans-conductance generation factor (TGF), cut-off frequency (f_T), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.     

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (g_m), output conductance (g_d), Early Voltage (V_EA), Maximum Transducer Power Gain, cut-off frequency (f_T), and I_on/I_off ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable I_on of~31.8 μA/μm and saturation transconductance g_m of~68.2 μS with improved third order derivative of transconductance g_m3.     

Comparative analysis of accelerated ageing effects on power RF LDMOS reliability

We present in this paper results of comparative reliability study of three accelerated ageing tests applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test), Thermal Cycling Tests (TCT, air-air test) and High Temperature Storage Life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The results obtained show the variation and the Device’s performance quantitative shifts for some macroscopic electric parameters such as threshold voltage (V_th), transconductance (G_m), drain-source current (I_ds), on-state resistance (R_{ds_on}) and feedback capacitance (C_rs) under various ageing tests. To understand the degradation phenomena that appear after ageing, we used a new electro-thermal model implemented in Agilent’s ADS as a reliability tool.     

Performance and optimisation of dual material gate short channel BULK MOSFETs for analogue/mixed signal applications

The challenge of analogue operation of CMOS devices and its parameters is a very important study for future technologies. In this article, the performance of dual material gate bulk MOSFETs for analogue/mixed signal applications is explored. Moreover, the optimisation of the device is done based on the variation of length and work-function difference of the two gate metals. The effect of drain induced barrier lowering in this structure is studied in detail. Moreover the different analogue parameters such as transconductance (g _m), output resistance (R _o) tuning for high performance of the device are also investigated by extensive simulations.     

Switched-current circuits test using pseudo-random method

A built in Pseudo-Random sequence testing for testing embedded switched-current filters is described in this paper. The generation approach of Pseudo-Random sequence and the match for z functions of switched-current filters is analyzed and calculated. Taking into account of the connection between special structural problems and CMOS’s parameters in switched current circuits such as the drain-gate capacitance C _dg , gate-source capacitance C _gs and transconductance g _m., a integrated fault model for testing is constituted. A 6-order switched-current low-pass filter has been tested based on catastrophic and parametric fault models. The technique does not intrude into the actual design of the switched-current blocks, Pseudo-Random sequence generated from existing digital hardware and analogue output pins are not required.     

Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs

Symmetric Dual-k Spacer (SDS) Hybrid FinFETs is a novel device, which combines three significant technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. For the first time, this article systematically analyzes the impacts of non-rectangular fin shape on various performance metrics of SDS Hybrid FinFETs. Under distinctive inclination fin angles as prescribed by the process technology, the performances of the device at different fin heights are examined. This work evaluates the response of fin tapering as well as fin height on parameters like threshold voltage (V_th), subthreshold slope (SS), on current (I_on), transconductance (g_m), transconductance generation factor (TGF), and total gate capacitance (C_gg) in SDS Hybrid FinFETs. Optimum structural configuration is thus proposed to fabricate the hybrid device in sub-20 nm FinFET architecture.     

Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET

In this paper, the performance of asymmetric underlapped FinFETs (U-FinFETs) is analyzed for linearity and harmonic distortion at high temperatures. The harmonic distortion that arises as a result of non-linear device characteristics requires a detailed analysis for better RF reliability performance. The variations in linearity and distortion characteristics with temperature are analyzed with regards to the primary components of harmonic distortion, second order distortion (HD2), third order distortion (HD3), and the total harmonic distortion (THD). For detailed understanding of the distortion characteristics of U-FinFETs, different device parameters such as the drain current (I_ds) and transconductance (g_m) are also analyzed. The results of the analysis suggest that the U-FinFETs present a significant reduction in harmonic distortion at elevated temperatures under subthreshold regime and restrict the degradation in harmonic distortion in the superthreshold regime resulting in better reliability for RF applications.