An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)

The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and inductor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of charge flowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, and hence can be used for non-volatile memory applications. Researchers have been exploring memristors from various perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture for the efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristor aided logic (MAGIC) design style. A Boolean function is first represented as a Binary Decision Diagram (BDD). The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbar architecture with parallel node evaluation where possible. This is the first approach that combines BDD-based synthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-related problems using a slicing architecture. Experimental evaluations on standard benchmark functions show considerable improvement in the solutions.     

石墨烯基电子学研究进展

综述了石墨烯晶体的能带结构和独特的电子性质,如双极性电场效应、单双层石墨烯效应、衬底效应、石墨烯纳米带(GNR)带隙等特殊效应的研究现状。介绍了石墨剥落技术、外延生长和化学气相淀积(CVD)等石墨烯材料的制备以及表征方法。列举了石墨烯在电子、显示、太阳电池、传感器和氢存储等方面的应用,如在石墨烯场效应管、石墨烯纳米带场效应管(SET)、石墨烯单电子晶体管、石墨烯金属晶体管、石墨烯基纳米电子机械系统(NEMS)、石墨烯分子开关以及石墨烯基高电子迁移率晶体管(HEMT)制备方面的应用。人们已经研究出不同栅长的n/p型顶栅石墨烯场效应管(GFET),并采用标准的S参数直接表征器件的高频性能。理论和实验表明,所有石墨烯纳米带场效应管(GNRFET)在室温下工作的前提是GNR的带宽尺寸小于10nm,并具有半导体场效应管的性能。     

Analysis of read speed latency in 6T-SRAM cell using multi-layered graphene nanoribbon and cu based nano-interconnects for high performance memory circuit design

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperature-dependent Cu and multilayered graphene nanoribbon (MLGNR)-based nano-interconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.     

Crosstalk bandwidth and stability analysis in graphene nanoribbon interconnects

Based on transmission line modeling (TLM), and using the Nichols chart, we present a bandwidth and stability analysis, together with step time responses, for coupled multilayer graphene nanoribbon (MLGNR) interconnects that is inquired for the first time. In this analysis, the dependence of the degree of crosstalk relative stability for coupled MLGNR interconnects comprising of both capacitive and mutual-inductive couplings between adjacent MLGNR has been acquired. The obtained results show that with increasing the length or decreasing the width of the MLGNRs, the stability in near-end output increases. While, any increase in the length or width of MLGNRs, decrease the stability of far-end output. Also, by increasing capacitive coupling or decreasing inductive coupling, the near-end output becomes more stable, and the far-end output becomes less stable. Moreover, any increase in the length or capacitive coupling, decreases the bandwidth, whereas any increase in the width or inductive coupling, increases the bandwidth. Finally, transient simulations with Advanced Design System (ADS) show that the model has an excellent accuracy.     

GNRFET双极特性及工作区域研究

石墨烯器件作为下一代纳米电子器件的有力竞争者受到广泛关注,但对其器件工作机理的研究尚不透彻。对石墨烯纳米带场效应晶体管(graphene nanoribbon field effect transistor,GNRFET)的双极特性进行了研究,分析了偏置电压对GNRFET转移特性和输出特性的影响,发现除已被关注到的栅电压外,源漏电压对GNRFET的双极特性亦有作用,并将两者综合考虑才能全面反映GNRFET的工作状态。在此基础上,进一步提出了工作区域的概念,将GNR-FET的工作区域划分为空穴导电区、电子导电区、转变区和截止区,为GNRFET器件的应用和电路设计提供指导。     

Ultra low power DG FinFET based voltage controlled oscillator circuits

Voltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations.     

A concept of analog-digital merged circuit architecture for future VLSI's

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-m devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5–0.2 m scaled CMOS devices.     

DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR

This paper presents a design method of ByPassing Unit（BPU） in 32-bit Digital Signal Processor（DSP）-MD32. MD32 is realized in 0.18 μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer（RISC） architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP＇s performance. The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.     

基于氧化石墨烯与金属离子的逻辑模型设计与可控性验证

作为20世纪末诞生的新型学科,生物计算现已成为前沿科学研究的热点。与电子计算机相似,生物计算机的构建需要多种分子逻辑门,而将氧化石墨烯(GO)、重金属离子等具有生化特性的物质引入分子逻辑门的设计中,有望为研究提出新思路。此外,分子逻辑门最终应在生物实验层面上实现,这就需要对生物实验各个条件的可控性及可控范围进行研究。基于这样的想法,该文以氧化石墨烯和金属离子为基础设计了多个逻辑门,通过仿真实验、电泳实验、正交实验、荧光实验等验证可行性的同时,对实验的可控性及可控范围有进一步研究,一方面证明了所设计逻辑门可行性,另一方面也发现其有运用于实际样品检测的能力。     

A power controlled interference aware routing protocol for dense multi-hop wireless networks

A key issue impacting the performance of multi-hop wireless networks is the interference among neighboring nodes. In this paper, we propose a novel and practical interference aware metric, termed as Network Allocation Vector Count (NAVC), to estimate the effects of the interference on the average delay and the available bandwidth. This metric can be easily applied to routing protocols designed for 802.11 based multi-hop networks with no modification to the current 802.11 protocol. The design of NAVC as a metric for the AODV [32] routing protocol, as well as a metric for transmit power control, are described in detail. Our simulation results reveal that the NAVC-driven AODV can greatly improve its performance compared to those protocols based on hop-count. For scenarios of densely deployed nodes, the throughput improvement is often a factor near two, indicating that NAVC is more useful as networks grow denser. Moreover, the network lifetime can be notably prolonged when the NAVC is employed to conduct transmit power control. Our approach is essential for emerging applications such as wireless sensor networks where the interference is heavy and the energy is severely constrained.     

Current status of CMOS low voltage and low power wireless IC designs

This paper surveys recent research on CMOS low voltage and low power IC designs for wireless applications. Advancements and challenges in using nanometer IC processes are addressed, and the impacts of device scaling on wireless systems are discussed. Recent advances in device technologies and system architectures are presented. State-of-the-art low power wireless systems, both from academia and from industry, are summarized. Circuit design techniques and challenges for low voltage and low power applications are discussed, along with RF performance and power trade-offs. Examples of common RF building blocks, e.g. LNA's and VCO's, designed for sub-1V power supplies are presented.     

边积分边读出低噪声红外焦平面读出电路研究

设计了一款低噪声InGaAs焦平面读出电路.提出一种新型相关双采样电路结构,可在边积分边读出模式下有效抑制积分电容(0.15 pF)的KTC噪声.电路经0.5 μn5 V Nwell CMOS工艺流片,测试结果符合设计目标,在高帧频边积分边读出模式下工作状态良好,电路噪声约1.7×10-4V,动态范围大于80 dB.     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

A beam steering antenna for X-band high power applications

There is a considerable interest in the antennas which have high power handling capacity with beam steering functionality. The design of narrow side waveguide slot-array antenna for high power applications is introduced in this paper. An approach to achieve a uniform radiation slot waveguide antenna is presented. The large scale array antenna can be composed of such antenna cells. Moreover, it is possible to realize beam steering in the azimuth direction by adjusting the broad wall dimension of the waveguide. Besides, this slot waveguide antenna is expected to have high power handling capacity in vacuum environment, because there is no dielectric or electric field enhancement inside the antenna.     

低功耗有源UHF-RFID标签芯片

采用SMIC 0.18 μm CMOS工艺,设计了一种低功耗的超高频有源RFID标签芯片射频接收前端电路.其中,低噪声放大器(LNA)采用共源共栅源极电感负反馈差分结构,下变频混频器(Mixer)采用吉尔伯特(Gilbert)有源双平衡结构.通过整体及模块电路优化,该电路在较低功耗下仍然具有较好性能.仿真结果表明,整个接收端功耗仅为14 mW,与传统射频前端芯片相比,功耗降低53%;整体增益为21.6 dB,噪声系数7.1 dB,三阶输入截止点-18.9 dBm,满足有源UHF-RFID标签芯片低功耗高性能的应用需求.     

Design of replica bit line control circuit to optimize power for SRAM

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.     

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45?nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I _on/I _off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO₂ (zirconium-di-oxide) is found out to be the best alternative for SiO₂ (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.     

3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture

A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application.     

Time-modulated multi-tone antenna array for wireless information and power transfer

This paper aims to design a multi-tone radiator exploiting harmonic radiation characteristic of time-modulated antenna array for wireless information and power transmission (WIPT) and multi-operational WIPT receiver. The time-modulated linear antenna array (TMLAA) radiating simultaneously at modulating and harmonic frequencies separated in multiple switching periods is utilized as a multi-tone radiating system. TMLAA with suitable power in harmonic bands generates multi-tone radiation by employing an optimized switching sequence. The ON and OFF time instants of the TMLAA are optimized to suppress sidelobe level and enhance sideband level. A population-based optimization algorithm, teaching learning based optimization (TLBO), is employed to optimize the ON and OFF instants of the TMLAA to suppress sidelobe level and enhance sideband level. TLBO is utilized for a 16-element TMLAA with minimizing cost function to achieve the above objectives. The 16-element TMLAA with optimized switching radiates multi-tone beams with a minimum of 5 dB peak power difference exploited as WIPT. The purpose of multi-operation is accomplished by utilizing the Wilkinson power divider in the receiver system; its power dividing capability is analyzed using applied wave research (AWR). A voltage doubler type rectifier is modeled for DC generation and is tested using AWR. The DC generating capability is tested for fixed power available at various frequencies, and the fixed desired frequency with various available power levels is tested. The results show that the designed circuitry provides a maximum of 80% power conversion efficiency (PCE).