Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

Influence of transient flow and solder bump resistance on underfill process

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60-70 μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.     

Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder

The choice of solder joint metallurgy is a key issue especially for the reliability of flip-chip assemblies. Besides the metallurgical systems already widely used and well understood, new materials are emerging as solderable under bump metallization (UBM). For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if single dies are available only and the chosen assembly technology is flip chip soldering. The scope of this paper is to summarize the results from aging of lead/tin solder bumps on palladium. The growth of intermetallic and its impact on the mechanical reliability are investigated.     

Experimental study of filling behaviors in the underfill encapsulation of a flip-chip

An underfill encapsulant was used to fill the gap between the chip and the substrate around the solder joints to improve the long-term reliability of the flip-chip interconnecting system. The underfill encapsulant was filled by the capillary effect. In this study, experiments were designed to investigate the effects of bump pitch and the edge detour flow on the underfill encapsulation. The bump array was patterned on a glass plate using the lithography technology. This patterned glass plate was used to simulate a flip-chip with solder bumps. The patterned glass was bounded to a substrate to form a simulated flip-chip system. With the lithography technology, it is easy to construct the test samples for underfill flow experiments with different configuration of solder bumps. It was observed that the filling flow was affected by the bump pitch. The edge detour flow depends mainly on the arrangement of the underfill dispensing process.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Three-Dimensional Thermomechanical Simulation of Fine-Pitch High-Count Ball Grid Array Flip-Chip Assemblies

Flip-chip technology is increasingly prevalent in electronics assembly [three-dimensional (3D) system-in-package] and is mainly used at fine pitch for manufacture of megapixel large focal-plane detector arrays. To estimate the reliability of these assemblies, numerical simulations based on finite-element methods appear to be the cheapest approach. However, very large assemblies contain more than one million solder bumps, and the optimization process of such structures through numerical simulations turns out to be a very time-consuming task. In many applications, the interconnection layer of such flip-chip assemblies consists of solder bumps embedded in epoxy filler. For such configurations, we propose an alternative approach, which consists in replacing this heterogeneous interconnection layer by a homogeneous equivalent material (HEM). A micromechanical model for the estimation of its equivalent thermoelastic properties has been developed. The obtained constitutive law of the HEM was then implemented in finite-element software (Abaqus^®). Thermomechanical responses of tested assemblies submitted to loads corresponding to manufacturing conditions have been analyzed. The homogenization–localization process allowed estimation of the mean values of stresses and strains in each phase of the interconnection layer. To access more precisely the stress and strain fields in these phases, two models of structural zoom, taking into account the real solder bump geometry, have been tested. The obtained local stress and strain fields corroborate the experimentally observed damage initiation of the solder bumps.     

Enhanced solder joint bonding strength of electronic packaging with electrowetting effect

This paper reports a novel method to enhance solder ball or solder ring bonding strength by using electrowetting-on-dielectric (EWOD) effect. With a low melting point, the metal Sn has been widely used in electronic packaging technology. Since Sn will be molten into liquid when the temperature is increased above the melting point, the method for treating liquid can be herein employed. Contact angle of the molten Pb-free balls or ring structure on silicon substrate have been experimentally changed by applying electric field across the thin dielectric film between the molten solder and the conductive silicon substrate. The contact area between the solder and the substrate is enlarged due to the decrease of the contact angle. Our testing results on the EWOD enhanced packaging structures of solder balls, flip-chip and solder ring hermetic package generally show about 50% enhancement in bonding shear strength. The significantly enhanced solder link bonding strength is hopeful for improving packaging reliability and is promising to be used in high performance silicon based electronic or microelectromechanic SiP (system in package) technologies.     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

Stacked solder bumping technology for improved solder joint reliability

Solder joint failure is a serious reliability concern in flip-chip and ball grid array packages of integrated-circuit chips. In current industrial practice, the solder joints take on the shape of a spherical segment. Mathematical calculations and finite element modeling have shown that hourglass-shaped solder joints would have the lowest plastic strain and stress during a temperature cycle, thus the longest lifetime. In an effort to improve solder joint reliability, we have developed a stacked solder bumping technique for fabricating triple-stacked hourglass-shaped solder joints. This solder bumping technology can easily control the solder joint shape and height. The structure of triple-stacked solder joints consists of an inner cap, middle ball and outer cap. The triple-stacked solder joints are expected to have greater compliance than conventional solder joints and are able to relax the stresses caused by the coefficient of thermal expansion mismatching between the silicon chips and substrates since it has a greater height. Furthermore, the hourglass-shaped solder joints are to have a much lower stress/strain concentration at the interface between the solder joint and the silicon die as well as at the interface between the solder joint and substrate than barrel-shaped solder joints, especially around the corners of the interfaces. In this paper, the solder bumping process is designed and joint reliability is evaluated. Mechanical tests have been carried out to characterize the adhesion strength of the solder joints. The interfaces of the solder joints are investigated by scanning electron microscopy and energy dispersive X-ray analysis. Temperature cycling results show that the triple-stacked hourglass-shaped solder joints are more reliable than the traditional spherical-shaped solder joints.     

凸点材料的选择对器件疲劳特性的影响

为了研究凸点材料对器件疲劳特性的影响,采用非线性有限元分析方法、统一型黏塑性本构方程和Coffin-Manson修正方程,对Sn3.0Ag0.5Cu,Sn63Pb37和Pb90Sn10三种凸点材料倒装焊器件的热疲劳特性进行了系统研究,对三种凸点的疲劳寿命进行了预测,并对Sn3.0Ag0.5Cu和Pb90Sn10两种凸点材料倒装焊器件进行了温度循环试验.结果表明,仿真结果与试验结果基本吻合.在热循环过程中,凸点阵列中距离器件中心最远的焊点,应力和应变变化最剧烈,需重点关注这些危险焊点的可靠性;含铅凸点的热疲劳特性较无铅凸点更好,更适合应用于高可靠的场合;而且随着铅含量的增加,凸点的热疲劳特性越好,疲劳寿命越长.     

Using scanning acoustic microscopy and LM-BP algorithm for defect inspection of micro solder bumps

Micro solder bump has been widely used in electronic packaging. Currently a number of flip-chip products are developing towards miniaturization with more I/Os at finer pitch, and defect inspection of the high density package is increasingly challenging. In this paper, the Levenberg-Marquardt back-propagation network (LM-BP) combined with the scanning acoustic microscopy technology was investigated for intelligent diagnosis of solder defect. The flip chips were detected by using a 230 MHz ultrasonic transducer. Solder bumps were segmented from the SAM image. The statistical features were extracted and fed into the LM-BP networks for bump classification. The results demonstrate that LM-BP algorithm reached a high recognition accuracy, and is effective for defect inspection of the micro solder bump.     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7/spl deg/C. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

Connection of VLSI chips to printed circuit board using stacked solder bumps

A new type of flip-chip interconnection technology usingstacked solder bumps is proposed, where the diameter of theupper solder bump is less than that of the lower ones. This isto reduce the capacitance between the stacked solder bumps and the ground plane and to prolong the lifetime ofthe solder joints.     

焊球植球凸块工艺的可靠性研究

焊球植球是一种最具潜力的低成本倒装芯片凸块制作工艺.采用焊球植球工艺制作的晶圆级芯片尺寸封装芯片的凸块与芯片表面连接的可靠性问题是此类封装技术研究的重点.为此,参考JEDEC关于电子封装相关标准,建立了检验由焊球植球工艺生产的晶圆级芯片尺寸封装芯片凸块与芯片连接及凸块本身是否可靠的可靠性测试方法与判断标准.由焊球植球工艺生产的晶圆级芯片尺寸封装芯片,分别采用高温存储、热循环和多次回流进行试验,然后利用扫描电子显微镜检查芯片上凸块剖面的凸块下金属层分布和测试凸块推力大小来验证凸块的可靠性.试验数据表明焊球植球工艺生产的晶圆级芯片尺寸封装芯片具有高的封装连接可靠性.     

A review of board level solder joints for mobile applications

The reliability of electronics under drop-shock conditions has attracted significant interest in recent years due to the widespread use of mobile electronic products. This review focuses on the drop-impact reliability of lead-free solder joints that interconnect the integrated circuit (IC) component to the printed circuit board (PCB). Major topics covered are the physics of failure in drop-impact; the use of board level and component level test methods to evaluate drop performance; micro-damage mechanisms; failure models for life prediction under drop-impact; modelling and simulation techniques; and dynamic stress–strain properties of solder joint materials. Differential bending between the PCB and the IC component is the dominant failure driver for solder joints in portable electronics subjected to drop-impact. Board level drop-shock tests correlate well with board level high speed cyclic bending tests but not with component level ball impact shear tests. Fatigue is the micro-damage mechanism responsible for the failure of solder joints in the drop-shock of PCB assemblies and the fatigue strength of solder joints depends strongly on the strain rate, test temperature, and the sequence of loading. Finally, tin-rich lead-free solders exhibit significantly higher strain rate sensitivity than eutectic SnPb solder.     

Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.     

Al surface morphology effect on flip-chip solder bump shear strength

This paper reports the result of a study on the effect of aluminum pad surface morphology on the flip-chip solder bump reliability. The influence of the Al surface morphology on the electroless zinc/nickel/gold UBM is presented. The reliability of the solder bump as measured by ball shear force is reported. Al pad were produced using two RF sputtering systems: CVC-601 and Varian-3180. The Al targets used in CVC and Varian system were 99%Al–1%Si and 98.95%Al–1%Si–0.05%Ti respectively. The surface of the CVC sputtered Al samples were smooth while the surface of the Varian sputtered Al samples were rough. All the samples were subjected to the electroless zinc/nickel/gold plating. The results suggest that after plating, the smooth Al surface resulted in a fine nickel UBM surface while the rough Al surface formed a coarse nickel UBM surface. Ball shear test was conducted after the solder balls were bumped on the UBM. Result shows that the fine UBM surface samples have twice the shear strength compared to the samples with coarse UBM surface samples. The analysis of the results indicates that shear surface occurred at the UBM and the solder interface for samples with rough UBM surface leading to the lower shear strength. Nickel bump shear test result shows that pretreatment of Al pad surface by sodium hydroxide and nitric acid created more zinc seeds this led to better electroless nickel plating. Nickel bump shear tests also shows that double zincated bumps had higher shear strength than single zincated bumps. To obtain reliable flip-chip solder bumps, it is essential to maintain good Al pad surface morphology, pretreatment of the Al pad and undergo second zincation.     

On the design parameters of flip-chip PBGA package assembly foroptimum solder ball reliability

An experimental investigation of the warpage of a flip-chip plastic ball grid array package assembly is presented and a critical deformation mode is identified. The experimental data, documented while cooling the assembly from the underfill curing temperature to -40°C, clearly reveal the effect of the constraints from the chip and the PCB on the global behavior of the substrate. The constraints produce an inflection point of the substrate at the edge of the chip. An experimentally verified three-dimensional (3-D) nonlinear finite element analysis proceeds to quantify the effect of the substrate behavior on the second-level solder ball strains. An extensive parametric study is conducted to identify the most critical design parameter for optimum solder ball reliability