A unified short-channel compact model for cylindrical surrounding-gate MOSFET

For the first time, a continuous and explicit model valid in all operating regions, for undoped short-channel cylindrical gate-all-around (GAA) MOSFETs, is presented in this study. From a two-dimensional analysis, the threshold voltage roll-off, the drain-induced barrier lowering (DIBL) and the subthreshold swing are explicitly modeled. Short-channel effects are then implemented into a continuous drain-current model based on an effective surface potential approach using the gradual channel approximation. Improving the model behavior in the saturation operating region by accounting the channel pinch-off displacement, channel length modulation is studied and implemented as well. Analytical results are compared to TCAD-Atlas numerical simulations and validate the short-channel model in all operating modes making it suitable for circuit design simulations.     

Analytic description of short-channel effects in fully-depleteddouble-gate and cylindrical, surrounding-gate MOSFETs

Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length λ, over which the source and drain perturb the channel potential, is 1/π of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs     

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.     

A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET’s

On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the short-channel tri-material gate-stack SOI MOSFET’s is developed. The model is verified by its good agreement with the numerical simulation of the device simulator MEDICI. The model not only offers physical insight into the device physics but also provides guidance for the basic design of the device.     

Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs

This paper reported the sub-threshold behavior of long channel undoped surrounding-gate (SRG) MOSFETs with respect to body radius. Based on a rigorous channel potential model presented in this work, the ideal room temperature subthreshold slope of 60 mV/dec can only be achieved when the silicon body radius is smaller than a critical value. With larger silicon body radius, SRG MOSFETs display a dual subthreshold slope of 60 mV/dec and 120 mV/dec. Based on the complex subthreshold characteristics, a new definition of threshold voltage together with an extraction method is adopted to investigate threshold voltage characteristics of undoped SRG MOSFETs in this paper.     

Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions

Physics-based analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions is presented. The effect of inversion carriers on the channel’s potential is considered in presented model. Using this analytical model, the characteristics of EJ-CSG are investigated in terms of surface potential and electric field distribution, threshold voltage roll-off, and DIBL. Results show that the application of electrically induced S/D extensions to the cylindrical surrounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, and DIBL. It is also revealed that a moderate side-gate bias voltage, a small gate oxide thickness, and a small silicon channel radius are needed to improve device characteristics. The derived analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.     

Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET

The subthreshold turnoff behavior of the long-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is characterized by the gate bias swingSneeded to reduce the subthreshold current one decade. Here a simple formula for S is derived which includes source-to-substrate reverse bias and ion-implanted doping profile effects. For uniformly doped structures it is shown that curves of givenScan be constructed on an oxide thickness versus doping level plot, making estimates ofSfor any choice of these parameters particularly simple. A separate family of curves is needed for each value of source-to-substrate bias VS. Source-to-substrate reverse bias greatly reduces S in devices with large S values, but cannot reduce S to its theoretical minimum value,S_{min} = (kT/q)ln 10, at reasonable values of VS. It is found that the effect of nonuniform doping is determined mainly by the dose and centroid of the depleted portion of the excess surface doping, provided buried channels do not occur and provided the implant is not primarily located in the inversion layer itself. Higher doses and deeper implants increaseS. The maximum value ofSfor a given implant dose and source-to-substrate reverse bias occurs for that range of implantation which places the implant near the depletion edge. Consequently, the use of implants in small MOSFET's to control threshold punchthrough and parasitic capacitances will cause turnoff degradation.     

Drain current model for short-channel triple gate junctionless nanowire transistors

This work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionless charge density in both accumulation and depletion regimes of operation, leading to a continuous model in all operational regions. The triple gate structure is modeled from an evolution of a previous model designed for double gate junctionless nanowire transistors (2G JNT). Improvements concerning the capacitance coupling, the internal potential changing while reducing the fin height in nanowire transistors and higher immunity to short-channel effects (SCE) are considered. The model validation is performed through both tridimensional numerical simulation and experimental measurements for long and short-channel devices. Through simulated results, it is verified the agreement of the modeled curves for junctionless transistors with different values of fin height. Comparison between the proposed model and experimental data is performed for 3G JNT advanced structures with channel length down to 15 nm and fin height of 8 nm. Results for 3G JNTs with different values of doping concentration and channel width are also displayed showing a good agreement as well. Moreover, 3G JNT performance is also analyzed and compared in the studied structures by extracting the threshold voltage (V_TH), subthreshold slope (S), DIBL and model parameters.     

Experimental determination of short-channel MOSFET parameters

In this paper we present a new method of determining the principal parameters for short-channel MOSFET modelling: V_T, μ₀, θ, ΔL and R_SD. They are deduced from the experimental curves I_D(V_G) (for small drain voltages) and I_D(V_D) (for relatively large gate voltages) curves. The main assumption is that the devices fabricated on the same silicon chip have the same technological reduction of transistor channel length and the same series resistance of source and drain. Our method takes advantageously into account (a) a new accurate determination of the threshold voltage and (b) the variation of the low-field mobility with channel length. Results obtained by applying this method to short-channel devices are given and discussed.     

Guidelines for reverse short-channel behavior

Necessary conditions for the occurrence of the reverse short-channel (RSC) effect for threshold voltage V_T for submicrometer MOSFETs due to channel profile nonuniformity are established: (1) sufficiently large concentration decrease towards the Si-SiO₂ interface of the channel doping (not necessarily a peak below the surface); (2) laterally nonhomogeneous enhancement of the diffusivity of the channel dopant either by injection of interstitials or vacancies from outside the gate region; and (3) the minimal distance between the point-defect injection next to the gate and the metallurgical channel-to-drain junction is smaller than the characteristic lateral decay length of the point defects. The above conditions are corroborated by the conditions for the threshold-voltage enhancement at the small channel lengths reported     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

短沟道MOS FET亚阈值电流的解析模型

利用二维泊松方程的解析解,得到了短沟道MOS FET亚阈值电流的解析模型.在弱反型区,解析模型的结果与数值模拟的结果符合较好.     

New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs

Using an exact solution of two-dimensional Poisson’s equation in cylindrical coordinates,a new analytical model comprising electrostatic potential,electric field,threshold voltage and subthreshold current for halodoped surrounding-gate MOSFETs is developed.It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide.It is also revealed that moderate halo doping concentration,thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics.The derived analytical model agrees well with a three-dimensional numerical device simulator ISE.     

Measurement and numerical modeling of short-channel MOSFET gate capacitances

The gate-to-source and gate-to-drain capacitance of long-and short-channel n-MOSFET's have been measured and simulated using a two-dimensional numerical simulator that allows different inversion layer carrier mobility models to be used. Comparison of the experimental and simulated data indicates velocity saturation effect is seen in the capacitance data of the short-channel devices. Transverse-field dependence of the mobility is also found to be necessary to account for the experimental data.     

Substrate bias dependence of short-channel MOSFET thresholdvoltage-a novel approach

A simple theory to predict the threshold voltage variation of short-channel MOS transistors with substrate bias is proposed. While the basis of the model is vertical field perturbations due to the source-drain, its uniqueness depends on a definition of threshold voltage based on the amount of total free charge in the channel rather than inversion of the entire channel. The theory has been verified for transistors of three channel lengths, namely 2.70, 1.70, and 0.70 μm, fabricated with a p-well CMOS process. A comparison is made with an earlier model based on field perturbation. The validity of the arguments underlying the theory has been demonstrated by 2-D device simulations with MINIMOS     

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.     

Threshold voltage theory for a short-channel MOSFET using a surface-potential distribution model

A detailed expression of the threshold voltage for a short-channel MOSFET is derived from a model of surface-potential distribution under the gate using a relationship of surface-channel charge neutrality. The theory is compared with the measured threshold voltages. The theoretical curves for threshold voltage over a wide range of drain and backgate voltage are in good agreement with experimental results. It is shown for a MOSFET having a channel length less than 2 μm that the body-bias constant increases as the drain voltage increases. The theory also predicts that the increase in backgate voltage leads to the reduction in short-channel effect for the shorter-channel case.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

Quantum mechanical influences on short-channel effects inultra-thin MOSFET/SIMOX devices

This paper describes an explicit manifestation of quantum-mechanical influences on the short channel effects (SCE) in the threshold voltage of ultra-thin buried-channel MOSFET/SIMOX devices. The theoretical model predicts an abnormal quantum mechanical SCE (QSCE) in extremely thin SOI layer. It also predicts that the QSCE becomes much salient at low temperatures, which is examined quantitatively by experiments     

A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator

A majority-carrier distribution model and a channel potential-profile model, in which the barrier-lowering effect is taken into account, are proposed for a buried-channel MOSFET (BC-MOSFET/ SOI). Simple expressions for threshold voltage and drain breakdown voltage were derived from the models for a short-channel BC-MOSFET/ SOI. The comparison between theory and experimental results shows reasonable agreement. The drain-bias coefficient γ of threshold voltage for BC-MOSFET's/ SOI is approximately proportional to TND^-1Leff^-2, where T, ND, and Leffare the temperature, the doping concentration in the channel region, and the channel length, respectively. The coefficient γ depends slightly on the drain bias. BC-MOSFET's/SOI are able to be more miniaturized than surface-channel MOSFET's (SC-MOSFET's) at the small power source voltage, and SC-MOSFET's are able to be more miniaturized than BC-MOSFET's/SOI at the large drain bias. It is shown that the conventional, simple scaling scheme, which holds the constant electric field, is not applicable to BC-MOSFET's/SOI. The power source voltage has to be fixed when dimensions and doping concentrations are scaled down. On the other hand, only the channel region thickness has to be fixed when the power source voltage is scaled down.