Channel length independent subthreshold characteristics insubmicron MOSFETs

This work reports an anomalous subthreshold characteristic of the MOSFET for the first time. It is observed that the subthreshold characteristic does not change as the channel length decreases. The cause of channel length independent subthreshold characteristics is identified as the localized pileup of channel dopants near the source and drain ends of the channel. The low surface potential of this pileup region limits the subthreshold current of MOSFET. As a result, the ratio of on-current to off-current for this MOSFET increases as the channel length is reduced, which is an important parameter for low-voltage operation. It is found that a MOSFET with channel length independent subthreshold characteristic is more suitable for low-voltage operation     

多晶硅薄膜晶体管亚阈值区准二维模型(英文)

从准二维泊松方程出发,结合多晶硅扩散和热发射载流子输运理论,建立了多晶硅薄膜晶体管亚阈值电流模型。由表面势方程及亚阈值电流方程求得包含陷阱态和晶粒尺寸的亚阈值斜率解析表达式。模型具有简明的表达式,并且在大晶粒和低陷阱态情形下可简化为传统长沟道MOSFET亚阈值区模型。仿真结果与试验数据符合得很好,验证了模型的正确性。     

短沟道MOS FET亚阈值电流的解析模型

利用二维泊松方程的解析解,得到了短沟道MOS FET亚阈值电流的解析模型.在弱反型区,解析模型的结果与数值模拟的结果符合较好.     

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.     

Analytical V TH and S models for (DMG–GC–stack) surrounding-gate MOSFET

This article presents an analytical model of surface potential, threshold voltage and subthreshold swing for a new structure of surrounding-gate MOSFET by combining dual-material gate, graded channel and gate stack. By comparison with published results, it is shown that the new MOSFET structure can improve the immunity of CMOS-based devices in the nanoscale regime against short-channel effects.     

A new approach to analytically solving the two-dimensional Poisson's equation and its application in short-channel MOSFET modeling

An analytical solution for the potential distribution of the two-dimensional Poisson's equation with the Dirichlet boundary conditions has been obtained for the MOSFET device by using Green's function method and a new transformation technique, in which the effects of source and drain junction curvature and depth are properly considered. Based on the calculated potential distribution, the subthreshold current considering the drain-induced barrier lowering effects has been computed by a simple current equation that considers only the diffusion component with an effective length determined by the potential distribution at the SiO2-Si interface. From the calculated subthreshold current, the threshold voltage of the MOSFET's is determined. It has been verified that the dependences of the calculated threshold voltage and subthreshold current on device channel length, drain, and substrate biases are in good agreement with those computed by whole two-dimensional numerical analysis and experimental data.     

A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions

An analytical subthreshold surface potential model for short-channel MOSFET is presented. In this model, the effect of varying depth of the channel depletion layer on the surface potential has been considered. The effect of the depletion layers around the source and drain junctions on the surface potential, which is very important for short channel devices is included in this model. With this, the drawback of the existing models that assume a constant channel depletion layer thickness is removed resulting in a more accurate prediction of the surface potential. A pseudo-two-dimensional method is adopted to retain the accuracy of two-dimensional analysis yet resulting in a simpler manageable one-dimensional analytical expression. The subthreshold drain current is also evaluated utilizing this surface potential model.     

FinFET design considerations based on 3-D simulation and analytical modeling

Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.     

Threshold and subthreshold characteristics theory for a very small buried-channel mosfet using a majority-carrier distribution model

Simple expressions of threshold and subthreshold characteristics for a very small buried-channel MOSFET is derived from a model of majority-carrier distribution along the channel. The carrier distribution is determined from the Poisson equation for a high-low junction. The basic formula for the subthreshold characteristic is derived from the majority-carrier drift-current equation. The theory is compared with the measured threshold voltages and the measured inverse semilogarithmic slopes of subthreshold current. The theoretical curves are in a reasonable agreement with experimental results. It is shown for a buried-channel MOSFET having a channel length less than 1 μm that the threshold and subthreshold characteristics change abruptly as the channel length is reduced because the majority-carrier concentration increases through the carrier diffusion from the source and drain terminals. The theoretical estimation shows that buried-channel MOSFETs will have the less short-channel effect than surface-channel MOSFETs for a small drain voltage. The theory also predicts that the buried-channel MOSFET can be scaled down in the same way as the surface-channel MOSFET.     

Double gate-MOSFET subthreshold circuit for ultralow power applications

In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance.     

An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs

An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Two-dimensional Poisson equation is solved analytically using series method and channel potential is obtained. The analytical expression for subthreshold swing is achieved. Model results are compared with Medici simulation results, both of them turn out to agree very well. The results show the variation of channel potential and subthreshold swing with channel length, gate bias, and oxide thickness, which will provide some guidance for the integrated circuit designs.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions

In this paper, we have introduced an analytical subthreshold and strong inversion 3D potential model for rectangular gate (RecG) gate-all-around (GAA) MOSFET. The subthreshold and strong inversion potential distribution in channel region of a RecG MOSFET is obtained respectively by solving 3D Laplace and 3D Poisson equations. The assumed parabolic potential distribution along the z-axis in channel direction is appropriately matched with 3D device simulator after consideration of z-depended characteristic length in subthreshold region. For accurate estimation of short channel effects (SCE), the electrostatics near source and drain is corrected. The precise gate-to-gate potential distribution is obtained after consideration of higher order term in assumed parabolic potential profile. The model compares well with numerical data obtained from the 3D ATLAS as a device simulator and deckbuild as an interactive runtime of Silvaco Inc.     

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs. Different short channel field effects, such as fringing fields, junction-induced lateral fields and substrate fields, are carefully investigated, and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model. Through analytical model-based simulation, the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations. Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model. The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET. The short channel effects are found to be reduced in an SON, thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope. This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.     

Effects of the velocity saturated region on MOSFET characteristics

A simple, accurate and universal relationship between MOSFET drain current in saturation, effective channel length, and gate drive has been found. It can be explained by a simple analytical model, whose validity is supported by numerical simulation. The model shows that the length of a velocity saturated region is a crucial parameter for describing MOSFET performance, particularly for short channel devices. The shrinkage of the length deteriorates the merit of channel length scaling     

Subthreshold transconductance in the long-channel MOSFET

The transconductance-current ratio of the long-channel MOSFET approaches the ideal value of q/kT under subthreshold conditions. This behavior has previously been explained using a BJT-like model. It is shown that such a model is inappropriate, and that this phenomenon can be explained by the diffusive nature of the subthreshold current, the law governing the density gradient, and the existence of a quasi high-low junction between the source region and channel. A general expression for subthreshold transconductance is developed. It is also demonstrated analytically that the bulk and inversion-layer capacitances that enter into this expression are equal at the threshold of strong inversion, a demonstration that avoids approximations employed in a previous treatment of the matter.     

A 2D sub-threshold current model for single halo triple material surrounding gate (SHTMSG) MOSFETs

In the proposed work analytical modeling of single halo triple material surrounding gate (SH-TMSG) MOSFET is developed. The threshold voltage and subthreshold current has been derived using parabolic approximation method and the simulation results are analyzed. The threshold voltage roll off is reduced and it denotes the deterioration of short channel effects. The results of the analytical model are delineated and compared with MEDICI simulation results and it is well corroborated.     

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.     

An optimized junctionless GAA MOSFET design based on multi-objective computation for high-performance ultra-low power devices

An analytical investigation has been proposed to study the subthreshold behavior ofjunctionless gates all around （JLGAA） MOSFET for nanoscale CMOS analog applications. Based on 2-D analytical analysis, a new subthreshold swing model for short-channel JLGAA MOSFETs is developed. The analysis has been used to calculate the subthreshold swing and to compare the performance of the investigated design and conventional GAA MOSFET, where the comparison of device architectures shows that the JLGAA MOSFET exhibits a superior performance with respect to the conventional inversion-mode GAA MOSFET in terms of the fabrication process and electrical behavior in the subthreshold domain. The analytical models have been validated by 2-D numerical simulations. The proposed analytical models are used to formulate the objectives functions. The overall objective function is formulated by means of a weighted sum approach to search the optimal electrical and dimensional device parameters in order to obtain the better scaling capability and the electrical performance of the device for ultra-low power applications.     

2D analytical calculation of the electric field in lightly doped Schottky barrier double-gate MOSFETs and estimation of the tunneling/thermionic current

In this paper we present a new approach to calculate the channel electric field within a Schottky barrier Double-Gate MOSFET (SB-DG-MOSFET) in subthreshold region by solving Poissons equation. The Poisson equation is solved two dimensionally in an analytical closed-form with the conformal mapping technique. A comparison with data simulated by TCAD Sentaurus simulator for channel lengths down to 22 nm was made and shows an accurate agreement. Futhermore, a new way for the estimation of the tunneling current in SB-DG-MOSFET by applying the above 2D solution for the electric field and a 2D solution of the electrostatic potential is presented. Calculating the tunneling current, we use Wentzel-Kramers-Brillouin (WKB) approximation for the estimation of the tunneling probability. For the calculation of the tunneling and thermionic current a comparison with TCAD Sentaurus for channel lengths down to 65 nm was made.