Novel low-voltage low-power full-swing BiCMOS circuits

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported     

A self-biased feedback-controlled pull-down emitter follower forhigh-speed low-power bipolar logic circuits

A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the emitter-follower input from the logic stage. Simulation results based on a 0.5-μm advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively     

Pull-down transient-imposed extrinsic base consideration in BiNMOStransistors

A detailed two-dimensional numerical simulation study of the bipolar devices in the BiCMOS circuit environment during pull-down transients is presented. The charge buildup and removal phenomenon in the bipolar device determines the switching speed of the BiNMOS devices. The tradeoffs in designing the extrinsic base in terms of the switching behavior are also described. It is shown that the structure with the extrinsic base p⁺ area farthest from the intrinsic base area has the best switching speed owing to the largest initial overshoot in the base voltage and the lateral base effects     

Study of BiCMOS logic gate configurations for improved low-voltageperformance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10°C and sub-2 V at 110°C     

A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable forVLSI using low-voltage BiCMOS technology

This paper presents a 1.5 V full-swing BiCMOS dynamic logic gate circuit, based on a dynamic pull-down BiPMOS configuration, suitable for VLSI using low-voltage BiCMOS technology. With an output load of 0.2 pf, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one     

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

This paper proposes a novel low-leakage BiCMOS deep-trench (DT) diode in a 0.18-/spl mu/m silicon germanium (SiGe) BiCMOS process. By means of the DT and an n/sup +/ buried layer in the SiGe BiCMOS process, a parasitic vertical p-n-p bipolar transistor with an open-base configuration is formed in the BiCMOS DT diode. Based on the two-dimensional (2-D) simulation and measured results, the BiCMOS DT diode indeed has the lowest substrate leakage current as compared to the conventional p/sup +//n-well diode even at high temperature conditions, which mainly results from the existence of the parasitic open-base bipolar transistor. Considering the applications of the diode string in electrostatic discharge (ESD) protection circuit designs, the BiCMOS DT diode string also provides a good ESD performance. Owing to the characteristics of the low leakage current and high ESD robustness, it is very convenient for circuit designers to use the BiCMOS DT diode string in their IC designs.     

A 1.5-V differential cross-coupled bootstrapped BiCMOS logic forlow-voltage applications

Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC²B-BiCMOS) and differential cross-coupled BiCMOS (DC²-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS buffer circuit structure is used to achieve high-speed operation under low supply voltage. Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed DC²B-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs. HSPICE simulation results have shown that the new DC²B-BiCMOS at 1.5 V and the new DC²-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input DC²B-BiCMOS XOR/XNOR gate chain fabricated by 0.8 μm BiCMOS technology that the speed of DC²-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed DC²B-BiCMOS and DC²-BiCMOS logic circuits are feasible for low-voltage, high-speed applications     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

An advanced PNP bipolar transistor design for a low-power and very-high-performance quarter-micron CBiCMOS process

This paper describes an advanced PNP bipolar transistor which has been designed by using the mixed two-dimensional device/circuit simulation (CODECS) [1] for a low-power and very-high-performance 0.25 μm complementary BiCMOS (CBiCMOS) device. The optimized PNP structure has a 30-nm-wide emitter, a 39-nm-wide intrinsic base region, a maximum cut-off frequency of 14 GHz and a current gain of 16 (without poly-Si emitter effect). A high performance and limits in terms of delay for pull-down of 0.25 μm CBiCMOS were obtained and compared to those offered by BiCMOS and complementary metal-oxide semiconductor circuits at different power supplies and charge capacitance. An improvement of 1.5 × at 1 pF, 1.6 × at 0.6 pF and 2 × at 0.2 pF over BiCMOS has been achieved.     

A wideband high-CMRR single-ended to differential converter

A novel circuit topology that provides wideband single-ended to differential conversion is presented. The proposed circuit exploits a negative feedback loop to generate a second input signal for a differential pair, thus obtaining 6 dB extra conversion gain and higher CMRR with respect to a simple differential pair driven single-ended. A signal and noise model for the circuit is proposed, based on admittance parameters and the use of a novel analysis technique to open the feedback loop while maintaining closed loop loading effects. The model is exploited to derive design guidelines in bipolar and MOS technologies. Measurements on a test chip in STMicroelectronics BiCMOS7 technology are reported to compare the performance of the proposed topology and of a simple differential pair used as single-ended to differential converter.     

An accurate analytical BiCMOS delay expression and its applicationto optimizing high-speed BiCMOS circuits

A scheme for optimizing the overall delay of BiCMOS driver circuits is proposed in this paper. Using this optimization scheme, it is found that the delay is minimized when the maximum collector current of the bipolar transistors is equal to the onset of high current effects. Using this assumption, an accurate BiCMOS delay expression is derived in terms of the bipolar and MOS device parameters. The critical device parameters are then identified and their influence on the circuit speed discussed. An overall circuit delay expression for optimizing BiCMOS buffers is derived and a comparison made with CMOS buffers. It is shown that BiCMOS circuits have a speed advantage of 1.7 or an area advantage of about 5 for 2-μm feature sizes. In order to predict the future performance of BiCMOS circuits, a figure of merit is derived from the delay expression. Using the figure-of-merit expression, it is seen that future BiCMOS circuits can keep the speed advantage over CMOS circuits down to submicrometer dimensions under constant load capacitance assumption     

一种新颖的高性能带隙基准的设计与分析

提出了一种新颖的分段线性补偿带隙基准,该补偿技术通过巧妙地运用带隙输出电压与三极管开启电压VBE的关系来实现.电路设计中,考虑了基准电压的电源抑制特性、线性调整率、电路的稳定性、功耗、芯片面积等各方面的因素,使得该电路很适合工程应用.全电路由BiCMOS工艺实现,并通过HSPICE仿真.结果表明,基准输出电压约1.169 V,有效温度系数仅为2.1×10-6/℃;室温下,电源抑制比为63 dB@1 kHz,功耗70μW(3 V电源).     

Line terminating multiplexers for SDH optical networks

WDM and TDM systems are compared for the next generation of line terminating multiplexers operating at around 10 Gb/s. A byte-interleaving circuit configuration suitable for large-scale synchronous multiplexing in multiples of eight is proposed. A prototype terminal circuit for STM-64 multiplexing that uses BiCMOS, Si bipolar, and GaAs MESFET IC technologies is reported     

An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.     

CMOS-compatible lateral bipolar transistor for BiCMOS technology.II. Experimental results

For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of h_FE, BV_CEO, R _CS, f_Tmax, and r_bb', are 20, 7 V, 50 Ω, 6.3 GHz, and 450 Ω, respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

基于0．5μmCMOS工艺的一款新型BiCMOS集成运算放大器设计

为了提高运算放大器的驱动能力,依据现有CMOS集成电路生产线,介绍一款新型BiCMOS集成运算放大电路设计,探讨BiCMOS工艺的特点。在s_Edit中进行“BiCMOS运放设计”电路设计,并对其电路各个器件参数进行调整,包括M0s器件的宽长比和电客电阻的值。完成电路设计后,在Tspice中进行电路的瞬态仿真,插入CMOS,PNP和NPN的工艺库,对电路所需的电源电压和输入信号幅度和频率进行设定调整,最终在W—Edit输出波形图。在MCNC0．5μm工艺平台上完成由MOs、双极型晶体管和电容构成的运算放大器版图设计。根据设计的版图,设计出BiCMOS相应的工艺流程,并提取各光刻工艺的掩模版。     

NCMOS: a high performance CMOS logic

CMOS has been the mainstay technology for VLSI design for the last several years. However, recently, BiCMOS technology has been proposed for speed critical applications. In this paper we propose a new circuit structure called NCMOS, which employs a low Vt NMOS transistor in place of the bipolar transistor, and provides significantly higher speed than a conventional CMOS design. This is realized at the cost of only one extra masking step, compared to 4-5 extra masks for a full BiCMOS process     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中