Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

Procedure for design optimization of a T-cap flip chip package

In this study, a 1/4 three-dimensional finite element model of a T-cap flip chip package containing the substrate, underfill, solder bump, silicon die, metal cap and cap attachment was established to conduct thermo-mechanical reliability study during the flip chip fabrication processes. The applied thermal load was cooled from 183 °C to ambience 25 °C to determine the thermal stress and warpage during the curing period of solder ball mounting process. Under fixed geometry, two levels of underfill, metal caps and cap attachments were used to conduct the 2³ factorial design for determining reliable material combinations. The statistical tests revealed that the significant effects affecting the thermal stress were the underfill, metal cap, cap attachment and the interaction between the underfill and cap attachment. The metal cap, cap attachment and their interaction significantly affected the warpage. The proposed regression models were used to perform the surface response simulations and were useful in selecting suitable materials for constructing the package. This study provides a powerful strategy to help the designer to easily determine reliable packaging structures under various reliability considerations.     

倒装芯片封装技术及内部应力检测技术探析

当前,倒装芯片封装技术已经成为相关领域的主流方法,但由于芯片、基板、焊球、下填料等材料具有差异化的热膨胀系数,导致封装过程中极易引入热应力,不利于保持芯片的性能及其可靠性。采用有效方法能够对倒装封装过程中所产生的应力进行检测,对于完善封装参数,提高产品可靠性,具有重要的现实意义。     

Field reworkable underfill materials for flip chip on boardassemblies

Studies have shown that underfill encapsulation dramatically improves the solder joint fatigue reliability of flip chip on board (FCOB) assemblies. The lack of reworkability of the underfill after the product is in the field has limited the integration of FCOB into cost sensitive electronic products and the continued proliferation of the FCOB technology will depend on the development of reworkable underfill materials systems. This paper presents data that correlates reliability performance to mechanical properties for twelve field reworkable underfill materials from three different suppliers. Their respective properties, processing parameters, and reliability performances are compared to the qualified, commercially available high performance underfills. Techniques were developed to redress the printed wiring board (PWB) site to enhance the reworked FCOB assembly yield. In addition, reliability performance results and failure analysis observations were compared to the first time nonreworked assemblies     

Influence of temperature and humidity on adhesion of underfills for flip chip packaging

This paper systematically discusses the influence of temperature and humidity on the adhesion performance of underfill material (epoxy cured with acid anhydride), which was evaluated by die shear test after exposure to various conditions. The inherent adhesion strength between the underfill and passivation is not affected significantly by thermal cycling between -55/spl deg/C and 125/spl deg/C for 1000 cycles. The adhesion strength of underfill material decreases with the increase of test temperature in the investigated range, due to the decrease of modulus of the underfill with the increase of temperature. A sharp decrease in adhesion strength occurs as temperature increases toward the glass transition temperature of the underfill material. Adhesion strength of underfill with different passivation materials decreases after aging in a high temperature and high humidity environment. The extent of the decrease depends on underfill formulation and the hydrophilicity of the passivation material. Hydrophilic passivation such silicon oxide (SiO/sub 2/) and silicon nitride (Si/sub 3/N/sub 4/) shows much more severe adhesion degradation than hydrophobic passivation such as benzocyclobutene (BCB) and polyimide (PI). Adhesion degradation is slower than moisture diffusion. The adhesion stability for hydrophilic passivation can be successfully improved by use of a coupling agent such as silane that introduces stable chemical bonds at interface.     

Characterisation of chip-on-board and flip chip packaging technologies by acoustic microscopy

In recent years scanning acoustic microscopy (SAM) has been found to be a very successful technique when used in the microelectronics industry to evaluate, from a reliability perspective, standard plastic packaging technologies such as PQFP's, PLCC's, DIP's and SOP's. Very little research has been reported in the application of SAM as a technique for determining the quality and reliability of packaging technologies such as Chipon-Board (COB) and Flip Chip adhered devices, however. These areas will be addressed in this paper.     

Characterization of chip scale packaging materials

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is of primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on results of the modeling. CSP with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperatures encountered in typical package assembly and die attach processes. Also, a lead free solder is discussed based on the results of creep testing. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability and performance results of the u*BGA packages, and the lead free solder creep.     

The optimization design of bump interconnections in flip chip packages from the electrical standpoint

Flip chip technologies have rapidly progressed and widely used in concert with the high speed and small dimension trends in electronic devices. This study performed an optimization design of the bump geometries in order to achieve higher electrical performance. The bump interconnections were considered as partial four-bump system to derive the analytical solution of the characteristic impedance. The first incident voltage determined form the characteristic impedance of the bump was employed as the optimization objective function to reduce the response time delay in the binary command for maintaining the chip level efficiency. The genetic algorithm was used for the search routines to evaluate the optimal solutions of the bump geometries in this research. Two cases of power supply voltages were adopted to conduct the case studying in both air and underfill environments. The optimization results show that a powerful design window for bump interconnections is established.     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

层叠微芯片封装翘曲行为优化分析

本文以某汽车用芯片为研究对象,研究芯片封装过程结构翘曲优化问题.首先采用Taguchi正交实验设计,结合Moldflow 2016微芯片封装模拟软件,分析各因素对芯片封装过程结构翘曲影响程度及影响规律.选择对芯片翘曲影响较大的因素为响应试验因素,芯片翘曲值为响应目标,进行Box-Behnken试验设计,建立响应面试验因...     

Thermal-mechanical optimization of a novel nanocomposite-film typed flip chip technology

The paper aims at optimization of the residual thermal-mechanical behaviors of a novel Flip Chip (FC) technology during and after the fabrication process. In this study, we first introduce the novel adhesive-typed FC packaging technology, consisting of a nanocomposite film for anisotropic electrical conduction and a nonconductive paste (NCP) for developing NCP joints. In the optimization work, the material and geometry properties and the bonding process parameters are considered as the design parameters, and the constraints on the residual behaviors and the design parameters are included. To deal with the multi-criteria design optimization problem, an effective metamodeling-based design optimization scheme is applied, which integrates parametric finite element (FE) analysis, a response surface methodology (RSM) and an updating scheme. Moreover, to assess the residual behaviors, a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death-birth” meshing scheme is carried out. The validity of the process-dependent FE simulation methodology is confirmed through experiment. Finally, two design practices are performed, and the calculated optimal designs are compared with each other and with the original design.It turns out that the present optimization methodology can be very effective and robust in seeking the optimal design of the FC technology with a better residual thermal-mechanical performance after the NCP bonding process.     

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.     

热-电耦合下倒装芯片封装焊点的电迁移失效研究

热电交互作用下产生的电迁移现象成为倒装芯片封装关键的可靠性问题。建立了FCBGA(倒装芯片球栅陈列封装)三维封装模型,研究了热-电交互作用下倒装芯片互连结构中的温度分布、电流密度分布以及焦耳热分布;发现焊料凸点中存在严重的焦耳热和电流聚集现象;分析了焊料凸点中热点出现的原因,并发现热点在焊料凸点空洞形成过程中起到了关键作用。     

倒装芯片凸焊点的UBM

介绍了倒装芯片凸焊点的焊点下金属（UBM）系统,讨论了电镀Au凸焊点用UBM的溅射工艺和相应靶材、溅射气氛的选择,给出了凸焊点UBM质量的考核试验方法和相关指标。     

Laser-assisted bumping for flip chip assembly

A novel laser-assisted chip bumping technique is presented in which bumps are fabricated on a carrier and subsequently transferred onto silicon chips by a laser-driven release process. Copper bumps with gold bonding layers and intermediate nickel barriers are fabricated on quartz wafers with pre-deposited polyimide layers, using UV lithography and electroplating. The bumps are thermosonically bonded to their respective chips and then released from the carrier by laser machining of the polyimide layer, using light incident through the carrier. Bumps of 60 to 85 μm diameter and 50 μm height at a pitch of 127 μm have been fabricated in peripheral arrays. Parallel bonding and subsequent transfer of arrays of 28 bumps onto test chips have been successfully demonstrated. Individual bump shear tests have been performed on a sample of 13 test chips, showing an average bond strength of 26 gf per bump     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

A hybrid optimization approach for chip placement of multi-chip module packaging

The aim of this article is to provide a systematic method to perform optimization design for chip placement of multi-chip module in electronic packaging. Based on the investigation of the structural and thermal characteristics of multi-chip module, the key performance indexes of multi-chip module that include the lowest internal temperature objective, thermal-transfer accuracy, chip placement are analyzed. A hybrid model is presented by using genetic algorithm and response surface methodology for optimization. Furthermore, some design processes for improving the performance are induced. Finally, an example is discussed to apply the method.     

Parametric compact models for flip chip assemblies

A parametric thermal compact modeling study of flip chip assemblies is presented. First, a star network of four thermal resistors was found to be optimal for a flip chip with arbitrary geometry and material properties. In a second step several parameters such as thermal underfill conductivity and die size were varied. The effect of these variations on the values of the four thermal resistors of the compact model is investigated. In a third step, a response surface model is derived from these compact models, which gives end-users the possibility of choosing a flip chip with arbitrary geometry and deduce automatically the corresponding thermal compact model. Having the compact model, it is now possible to apply customer specific boundary conditions to this compact model and compute the maximal temperature reached at the junction of the flip chip assembly in the specified environment     

Coaxial transitions for CPW-to-CPW flip chip interconnects

A novel coaxial transition for CPW-to-CPW flip chip interconnect is presented and experimentally demonstrated. To realise the coaxial transition on the CPW circuit, benzocyclobutene was used as the interlayer dielectric between the vertical coaxial transition and the CPW circuit. The coaxial interconnect structure was successfully fabricated and RF characterised to 67 GHz. The structure showed excellent interconnect performance from DC up to 55 GHz with low return loss below 20 dB and low insertion loss less than 0.5 dB even when the underfill was applied to the structure.