Deterministic BIST with Partial Scan

An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.     

Deterministic BIST with Multiple Scan Chains

A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage.The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.     

低成本BIST映射电路的设计与优化

低成本BIST利用映射电路对自测试线形反馈移位寄存器进行优化,将对故障覆盖率无贡献的测试向量屏蔽掉,有效提高了故障覆盖率,降低了测试功耗。映射电路的设计是低成本BIST设计的关键,为了降低其硬件开销和功耗、提高参数性能,该映射逻辑电路对测试向量的种子进行映射,并通过相容逻辑变量合并、布尔代数化简等方法对映射电路进行优化,有效地降低了测试应用时间、测试功耗和硬件开销。     

FPGA逻辑资源重配置测试技术研究

针对FPGA的逻辑资源测试,提出了一种内建自测试方法.测试中逻辑资源划分为不同功能器件,对应各个功能器件设计了相应的BIST测试模板.在此基础上进一步利用FPGA的部分重配置性能优化BIST测试过程,最终在统一的BIST测试框架下,采用相对较少的配置次数完成了逻辑资源固定故障的全覆盖测试.     

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.     

A Ring Architecture Strategy for BIST Test Pattern Generation

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].     

逻辑内建自测移相器的设计与优化

逻辑内建自测(Logic BIST)测试结构是今后系统芯片(SOC)设计中芯片测试的发展方向。由于LFSR(线性反馈移位寄存器)生成的伪随机序列的高相关性导致故障覆盖率达不到要求，采用移相器可以降低随机序列的空间相关性，提高Logic BIST的故障覆盖率。本文分析了移相器的数学理论并提出了移相器设计与优化算法。该算法可以得到最小时延与面积代价下的高效移相器。     

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%.     

An Efficient Logic Equivalence Checker for Industrial Circuits

We present our formal combinational logic equivalence checking methods for industry-sized circuits. Our methods employ functional (OBDDs) algorithms for decisions on logic equivalence and structural (ATPG) algorithms to quickly identify inequivalence. The complimentary strengths of the two types of algorithms result in a significant reduction in CPU time. Our methods also involve analytical and empirical heuristics whose impact on performance for industrial designs is considerable. The combination of OBDDs, ATPG, and our heuristics resulted in a decrease in CPU time of up to 80% over OBDDs alone for the circuits we tested. In addition, we describe an algorithm for automatically determining the correspondence between storage elements in the designs being compared.     

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device after the test thus, allowing the use of the whole circuit by the user. The structure we propose is composed of a simple test pattern generator, an error detector and a chain of LUTs. The chain of LUTs is formed alternatively by a LUT and a flip–flop. By using such a chain, the test of all delay faults in every LUT is enabled. In this paper, we develop an experiment based on the implantation of our BIST architecture in a Virtex FPGA from Xilinx. The purpose of this experiment is to show the feasibility of our solution. As a result, one important issue from this solution is its ability to detect the “smallest” delay faults in the LUTs, i.e. the smallest delays that can be observed on a LUT output. Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Micro-electronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing, and low power testing. He has authored and co-authored more than 90 papers on these fields, and has supervised several PhD dissertations. He has also participated to several European research projects (Esprit III ATSEC, Eureka MEDEA, MEDEA+ ASSOCIATE, IST MARLOW). Patrick GIRARD holds a B.Sc. and a M.Sc. in Electrical Engineering, and obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992. Olivier Héron is presently researcher at CEA (French Center for Technology Research) in the laboratory of Reliability for Embedded Systems. His research interests are Logic BIST, On-Line Testing, Delay Fault Testing of FPGAs and Fault Modelling. He is a member of the program commitee of the Field Programmable Logic Conference FPL2006. He received his Ph.D. from the University of Montpellier (France) in 2004 and worked in the Microelectronics Department of the LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier—France). He received the B.Sc. degree in 1998 and the M.Sc. degree in 2001 in Electrical Engineering from the University of Montpellier. Serge Pravossoudovitch was born in 1957. He is currently Professor in the Electrical and Computer Engineering Department of the University of Montpellier and his research activities are performed at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier—France). He is received the Master degree in Electrical Engineering in 1979 from the University of Montpellier. He got his Ph.D. degree in Electrical Engineering in 1983 on symbolic layout for IC design. Since 1984, he was been interested in the testing domain. He obtained the “doctorat d’état” degree in 1987 for his works on switch level automatic test pattern generation. He is presently interested in delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, MEDEA). Michel Renovell is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee) and Chair of the FPGA testing Committee. He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of several conferences: International Mixed Signal Testing Workshop IMSTW2000, Field Programmable Logic Conference FPL2002 and European Test Symposium ETS2004. A preliminary version of this work has been presented at the 1st European Test Symposium 2004, in Ajaccio.     

一种基于扫描结构的混合模式BIST的低功耗设计

针对扫描结构混合模式BIST的特点,文章提出了一种利用双模式LFSR和新型折叠控制器相结合的方法来对基于扫描结构的混合模式BIST电路进行低功耗优化设计,从而达到降低待测电路功耗的目的.     

基于March X算法的SRAM BIST的设计

针对LS-DSP中嵌入的128kb SRAM模块,讨论了基于March X算法的BIST电路的设计.根据SRAM的故障模型和测试算法的故障覆盖率,讨论了测试算法的选择、数据背景的产生:完成了基于March X算法的BIST电路的设计.128kb SRAM BIST电路的规模约为2000门,仅占存储器面积的1.2%,故障覆盖率高于80%.     

一种嵌入式RAM的BIST设计

本文分析了嵌入式RAM的传统测试方法和内建自测试(BIST)方法,提出了一种新的BI ST设计方案,该设计方案具有测试生成快,节约测试成本等优点.     

EWB在《数字电路》教学中的应用

在数字电路教学中，运用EWB仿真软件，进行理论与仿真验证相结合的教学改革，快速地将理论变抽象为感性，克服了传统理论教学中的不足。     

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.     

遏止(Quenching)及其在分析RTD逻辑电路中的应用

在深入分析共振隧穿二极管(RTD)开关前后内阻变化和RTD串联组合中不同RTD电压分布随总偏压变化的基础上,深化了“遏止(Q uench ing)”的概念。并进一步以此概念说明了RTD/HEM T电路中,单-双稳转换逻辑单元(M OB ILE)、多值逻辑(M VL)文字(L itera l)逻辑门、三态反相器(T ernary inverter)等逻辑单元的工作原理。通过此种分析,证实了“遏止”概念是解释和分析复杂RTD电路原理的强有力工具。以上论证也适用于由其它负阻器件构成的逻辑电路。     

一种新的低功耗BIST测试生成器设计

文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的BIST测试生成器设计方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑电路,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低.由于该设计方案比其它LPTPG方案的面积开销小,从而具有更好的使用价值.     

基于硅基微环谐振器的光学导向逻辑器件

光学导向逻辑器件是采用光开关网络执行逻辑运算的典型应用,光学网络中每一个开关的状态由施加到该开关的电学布尔信号决定。网络中每一个光开关的操作都是独立于其他光开关的操作,并且操作运算结果以光速在网络中传播。因此,光学导向逻辑器件具有非常高的运行速度,且总延迟非常小。硅基微环谐振器由于其尺寸小、功耗低、与CMOS工艺兼容等特性成为构建光学导向逻辑器件的理想单元器件。基于硅基微环谐振器的光学导向逻辑器件很容易实现大规模集成和低成本制备,已经提出并实现的基于硅基微环谐振器的光学导向逻辑器件包括"或/或非"、"与/与非"、"异或/同或"、编码器、译码器和半加器等。回顾了本课题组基于硅基微环谐振器实现的光学导向逻辑器件的研究成果和该领域的最新发展。     

三种改进结构型BiCMOS逻辑单元的研究

为满足低压、高速、低耗数字系统的应用需求 ,通过采用改进电路结构和优化器件参数的方法 ,设计了三种改进结构型BiCMOS逻辑单元电路。实验结果表明 ,所设计电路不但具有确定的逻辑功能 ,而且获得了高速、低压、低耗和接近于全摆幅的特性 ,它们的工作速度比高速CMOS和原有的互补对称BiCMOS(CBiCMOS)电路快约一倍 ,功耗在 6 0MHz频率下仅高出 1 4 9～ 1 71mW ,但延迟 功耗积却比原CBiCMOS电路平均降低了4 0 3%。     

EWB在数字电路仿真分析中的应用

介绍了电路仿真软件ＥＷＢ（ Ｅｌｅｃｔｒｏｎｉｃｓ Ｗｏｒｋｂｅｎｃｈ）的数字逻辑电路仿真功能与实现方法。两个典型数字逻辑电路仿真分析实例表明ＥＷＢ为数字电路分析设计提供了实用、高效的仿真环境。