Self-organized growth of Si/Silica/Er2Si2O7 core-shell nanowire heterostructures and their luminescence

Self-organized Si-Er heterostructure nanowires showed promising 1.54 microm Er(3+) optical activity. Si nanowires of about 120-nm diameter were grown vertically on Si substrates by the vapor-liquid-solid mechanism in an Si-Er-Cl-H(2) system using an Au catalyst. Meanwhile, a single-crystalline Er(2)Si(2)O(7) shell sandwiched between nanometer-thin amorphous silica shells was self-organized on the surface of Si nanowires. The nanometer-thin heterostructure shells make it possible to observe a carrier-mediated 1.53 microm Er(3+) photoluminescence spectrum consisting of a series of very sharp peaks. The Er(3+) spectrum and intensity showed absolutely no change as the temperature was increased from 25 to 300 K. The luminescence lifetime at room temperature was found to be 70 micros. The self-organized Si nanowires show great potential as the material basis for developing an Si-based Er light source.     

Diameter-dependent composition of vapor-liquid-solid grown Si(1-x)Ge(x) nanowires

Diameter-dependent compositions of Si(1-x)Ge(x) nanowires grown by a vapor-liquid-solid mechanism using SiH(4) and GeH(4) precursors are studied by transmission electron microscopy and X-ray energy dispersive spectroscopy. For the growth conditions studied, the Ge concentration in Si(1-x)Ge(x) nanowires shows a strong dependence on nanowire diameter, with the Ge concentration decreasing with decreasing nanowire diameter below approximately 50 nm. The size-dependent nature of Ge concentration in Si(1-x)Ge(x) NWs is strongly suggestive of Gibbs-Thomson effects and highlights another important phenomenon in nanowire growth.     

Growth of GaInAs/AlInAs heterostructure nanowires for long-wavelength photon emission

We investigated the growth of GaInAs/AlInAs heterostructure nanowires on InP(111)B and Si(111) substrates in a metalorganic vapor phase epitaxy reactor. Au colloids were used to deposit Au catalysts 20 and 40 nm in diameter on the substrate surfaces. We obtained vertical GaInAs and AlInAs nanowires on InP(111)B surfaces. The GaInAs nanowires capped with GaAs/AlInAs layers show room-temperature photoluminescence. The peak exhibits a blue-shift when the Ga content in the core GaInAs nanowire is increased. For the GaInAs/AlInAs heterostructure growth, it is possible to change the Ga content sharply but Al also exists in the GaInAs layer regions. We also found that the ratios of Ga and Al contents to In content tend to increase and the axial growth rate to decrease along the nanowire toward the top. We were also able to make vertical GaInAs nanowires on Si(111) surfaces after a short growth of GaP and InP.     

Doping of Si into GaN nanowires and optical properties of resulting composites

Doping of Si into GaN nanowires has been successfully attained via thermal evaporation in the presence of a suitable gas atmosphere. Analysis indicated that the Si-doped GaN nanowire is a single crystal with a hexagonal wurtzite structure, containing 2.2 atom % of Si. The broadening and the shift of Raman peak to lower frequency are observed, which may be attributed to surface disorder and various strengths of the stress. The band-gap emission (358 nm) of Si-doped GaN nanowires relative to that (370 nm) of GaN nanowires has an apparent blue shift (approximately 12 nm), which can be ascribed to doping impurity Si.     

Single crystalline PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices

We report the formation of PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices from such heterostructures. Scanning electron microscopy studies show that silicon nanowires can be converted into PtSi nanowires through controlled reactions between lithographically defined platinum pads and silicon nanowires. High-resolution transmission electron microscopy studies show that PtSi/Si/PtSi heterostructure has an atomically sharp interface with epitaxial relationships of Si[110]//PtSi[010] and Si(111)//PtSi(101). Electrical measurements show that the pure PtSi nanowires have low resistivities approximately 28.6 microOmega.cm and high breakdown current densities>1x10(8) A/cm2. Furthermore, using single crystal PtSi/Si/PtSi nanowire heterostructures with atomically sharp interfaces, we have fabricated high-performance nanoscale field-effect transistors from intrinsic silicon nanowires, in which the source and drain contacts are defined by the metallic PtSi nanowire regions, and the gate length is defined by the Si nanowire region. Electrical measurements show nearly perfect p-channel enhancement mode transistor behavior with a normalized transconductance of 0.3 mS/microm, field-effect hole mobility of 168 cm2/V.s, and on/off ratio>10(7), demonstrating the best performing device from intrinsic silicon nanowires.     

In-situ TEM observation of repeating events of nucleation in epitaxial growth of nano CoSi2 in nanowires of Si

The formation of CoSi and CoSi2 in Si nanowires at 700 and 800 degrees C, respectively, by point contact reactions between nanodots of Co and nanowires of Si have been investigated in situ in a ultrahigh vacuum high-resolution transmission electron microscope. The CoSi2 has undergone an axial epitaxial growth in the Si nanowire and a stepwise growth mode was found. We observed that the stepwise growth occurs repeatedly in the form of an atomic step sweeping across the CoSi2/Si interface. It appears that the growth of a new step or a new silicide layer requires an independent event of nucleation. We are able to resolve the nucleation stage and the growth stage of each layer of the epitaxial growth in video images. In the nucleation stage, the incubation period is measured, which is much longer than the period needed to grow the layer across the silicide/Si interface. So the epitaxial growth consists of a repeating nucleation and a rapid stepwise growth across the epitaxial interface. This is a general behavior of epitaxial growth in nanowires. The axial heterostructure of CoSi2/Si/CoSi2 with sharp epitaxial interfaces has been obtained. A discussion of the kinetics of supply limited and source-limited reaction in nanowire case by point contact reaction is given. The heterostructures are promising as high performance transistors based on intrinsic Si nanowires.     

Band-gap modulation in single-crystalline Si1-xGex nanowires

We report the energy band-gap modulation of single-crystalline Si1-xGex (0 相似文献   

Interface charge induced p-type characteristics of aligned Si(1-x)Gex nanowires

This study reports the electrical transport characteristics of Si(1-x)Gex (x=0-0.3) nanowires. Nanowires with diameters of 50-100 nm were grown on Si substrates. The valence band spectra from the nanowires indicate that energy band gap modulation is readily achievable using the Ge content. The structural characterization showed that the native oxide of the Si(1-x)Gex nanowires was dominated by SiO2; however, the interfaces between the nanowire and the SiO2 layer consisted of a mixture of Si and Ge oxides. The electrical characterization of a nanowire field effect transistor showed p-type behavior in all Si(1-x)Gex compositions due to the Ge-O and Si-O-Ge bonds at the interface and, accordingly, the accumulation of holes in the level filled with electrons. The interfacial bonds also dominate the mobility and on- and off-current ratio. The large interfacial area of the nanowire, together with the trapped negative interface charge, creates an appearance of p-type characteristics in the Si(1-x)Gex alloy system. Surface or interface structural control, as well as compositional modulation, would be critical in realizing high-performance Si(1-x)Gex nanowire devices.     

Uniform and position-controlled InAs nanowires on 2" Si substrates for transistor applications

This study presents a novel approach for indirect integration of InAs nanowires on 2' Si substrates. We have investigated and developed epitaxial growth of InAs nanowires on 2' Si substrates via the introduction of a thin yet high-quality InAs epitaxial layer grown by metalorganic vapor phase epitaxy. We demonstrate well-aligned nanowire growth including precise position and diameter control across the full wafer using very thin epitaxial layers (<300 nm). Statistical analysis results performed on the grown nanowires across the 2' wafer size verifies our full control on the grown nanowire with 100% growth yield. From the crystallographic viewpoint, these InAs nanowires are predominantly of wurtzite structure. Furthermore, we show one possible device application of the aforementioned structure in vertical wrap-gated field-effect transistor geometry. The vertically aligned InAs nanowires are utilized as transistor channels and the InAs epitaxial layer is employed as the source contact. A high uniformity of the device characteristics for numerous transistors is further presented and RF characterization of these devices demonstrates an f(t) of 9.8 GHz.     

Composition and local strain mapping in Au-catalyzed axial Si/Ge nanowires

For most applications, heterostructures in nanowires (NWs) with lattice mismatched materials are required and promise certain advantages thanks to lateral strain relaxation. The formation of Si/Ge axial heterojunctions is a challenging task to obtain straight, defect free and extended NWs. And the control of the interface will determine the future device properties. This paper reports the growth and analysis of NWs consisting of an axial Si/Ge heterostructure grown by a vapor-liquid-solid process. The composition gradient and the strain distribution at the heterointerface were measured by advanced quantitative electron microscopy methods with a resolution at the nanometer scale. The transition from pure Ge to pure Si shows an exponential slope with a transition width of 21?nm for a NW diameter of 31?nm. Although diffuse, the heterointerface makes possible strain engineering along the axis of the NW. The interface is dislocation-free and a tensile out-of-plane strain is noticeable in the Ge section of the NW, indicating a lattice accommodation. Experimental results were compared to finite element calculations.     

Diameter-dependent growth direction of epitaxial silicon nanowires

We found that silicon nanowires grown epitaxially on Si (100) via the vapor-liquid-solid growth mechanism change their growth direction from 111 to 110 at a crossover diameter of approximately 20 nm. A model is proposed for the explanation of this phenomenon. We suggest that the interplay of the liquid-solid interfacial energy with the silicon surface energy expressed in terms of an edge tension is responsible for the change of the growth direction. The value of the edge tension is estimated by the product of the interfacial thickness with the surface energy of silicon. For large diameters, the direction with the lowest interfacial energy is dominant, whereas for small diameters the surface energy of the silicon nanowire determines the preferential growth direction.     

Growth of GaAs Nanowires on Si Substrates Using a Molecular Beam Epitaxy

Au-catalyzed GaAs nanowires were grown on Si substrates by vapor-liquid-solid growth method using a molecular beam epitaxy (MBE). The MBE growth could produce controlled crystalline orientation and uniform diameter along the wire axis of the GaAs nanowires by adjusting growth conditions including growth temperature and V/III flux ratio. Growths of GaAslang001rang as well as GaAslang111rang nanowires were observed by transmission electron microscopy and scanning electron microscopy. Epitaxially grown GaAslang111rang nanowires on a Si(111) substrate were verified through x-ray diffraction out-of-plane 2thetas/omega-scans. A strong room-temperature photoluminescence (PL) was observed from the epitaxially grown GaAslang111rang nanowires on a Si(100) substrate. Results of low-temperature (10 K) PL measurements and current-sensing atomic force microscopy indicated that the GaAs nanowires on a Si substrate were unintentionally doped with Si     

The oxides growth during high-temperature oxidation of Si1-xGe(x) nanowires

Concerning the oxidation behavior of Si1-xGe(x) (x = 0.15, 0.3) nanowires at high temperature, Si1-xGe(x) nanowires were thermally oxidized for various lengths of time compared with Si nanowires, Si and Si1-xGe(x) thin films. The structural and compositional properties of the oxidized nanowires were characterized using several transmission electron microscopy (TEM) techniques including energy dispersive X-ray spectroscopy (EDS), which confirm that the oxidation rates of Si1-xGe(x) and Si (silicon) nanowires were saturated with increasing oxidation time due to retarding behavior, while the oxidation rate of Si1-xGe(x) nanowires were faster than that of Si nanowires. In addition, the differences in Ge (germanium) content and stress distribution contribute to the observed differences in oxidation behavior.     

Synthesis of amorphous Si nanowires from solid Si sources using microwave irradiation

Si nanowires were synthesized from Si wafers and from thin Si films deposited on various substrates by microwave irradiation. The power and time were key determinants of the diameter and morphology of the synthesized Si nanowires. The nanowires had an amorphous structure due to the extremely high heating rate. Carbon coating of the Si nanowires was easily achieved by introducing acetylene after synthesizing the nanowires. Carbon-coated Si nanowires are potential candidates for use as the anode material in next generation Li-ion batteries.     

Composition controlled synthesis and Raman analysis of Ge-rich Si(x)Ge(1-x) nanowires

Here, we report the synthesis of Si(x)Ge(1-x) nanowires with x values ranging from 0 to 0.5 using bulk nucleation and growth from larger Ga droplets. Room temperature Raman spectroscopy is shown to determine the composition of the as-synthesized Si(x)Ge(1-x) nanowires. Analysis of peak intensities observed for Ge (near 300 cm(-1)) and the Si-Ge alloy (near 400 cm(-1)) allowed accurate estimation of composition compared to that based on the absolute peak positions. The results showed that the fraction of Ge in the resulting Si(x)Ge(1-x) alloy nanowires is controlled by the vapor phase composition of Ge.     

Ge oxidation in the remaining cores of Si(1-x)Ge(x) nanowires after prolonged oxidation

For this investigation of the Ge behavior of condensed Si(1-y)Ge(y) (y > x) cores during the oxidation of Si(1-x)Ge(x) nanowires, Si(1-x)Ge(x) nanowires were grown in a tube furnace by the vapor-liquid-solid method and thermally oxidized. The test results were characterized using several techniques of transmission electron microscopy. The two types of Ge condensation are related to the diameter and Ge content of the nanowires. The consumption of Si atoms in prolonged oxidation caused the condensed SiGe cores to become Ge-only cores; and the continuous oxidation resulted in the oxidation of the Ge cores. The oxidation of Ge atoms was confirmed by scanning transmission electron microscopy.     

The influence of surface oxide on the growth of metal/semiconductor nanowires

We report the critical effects of oxide on the growth of nanostructures through silicide formation. Under an in situ ultrahigh vacuum transmission electron microscope, it is observed from the conversion of Si nanowires into the metallic PtSi grains epitaxially through controlled reactions between lithographically defined Pt pads and Si nanowires. With oxide, instead of contact area, single crystal PtSi grains start forming either near the center between two adjacent pads or from the ends of Si nanowires, resulting in the heterostructure formation of Si/PtSi/Si. Without oxide, transformation from Si into PtSi begins at the contact area between them, resulting in the heterostructure formation of PtSi/Si/PtSi. The nanowire heterostructures have an atomically sharp interface with epitaxial relationships of Si(20-2)//PtSi(10-1) and Si[111]//PtSi[111]. Additionally, it has been observed that the existence of oxide significantly affects not only the growth position but also the growth behavior and the growth rate by two orders of magnitude. Molecular dynamics simulations have been performed to support our experimental results and the proposed growth mechanisms. In addition to fundamental science, the significance of the study matters for future processing techniques in nanotechnology and related applications as well.     

Growth of nickel silicides in Si and Si/SiOx core/shell nanowires

We exploited the oxide shell structure to explore the structure confinement effect on the nickel silicide growth in one-dimensional nanowire template. The oxide confinement structure is similar to the contact structure (via hole) in the thin film system or nanodevices passivated by oxide or nitride film. Silicon nanowires in direct contact with nickel pads transform into two phases of nickel silicides, Ni31Si12 and NiSi2, after one-step annealing at 550 °C. In a bare Si nanowire during the annealing process, NiSi2 grows initially through the nanowire, followed by the transformation of NiSi2 into the nickel-rich phase, Ni31Si12 starting from near the nickel pad. Ni31Si12 is also observed under the nickel pads. Although the same phase transformations of Si to nickel silicides are observed in nanowires with oxide confinement structure, the growth rate of nickel silicides, Ni31Si12 and NiSi2, is retarded dramatically. With increasing oxide thickness from 5 to 50 nm, the retarding effect of the Ni31Si12 growth and the annihilation of Ni2Si into the oxide confined-Si is clearly observed. Ni31Si12 and Ni2Si phases are limited to grow into the Si/SiOx core-shell nanowire as the shell thickness reaches 50 nm. It is experimental evidence that phase transformation is influenced by the stressed structure at nanoscale.     

Si nanowires synthesized with Cu catalyst

The metal copper which is a newly developed interconnecting material for integrated circuit (IC) has been used as the catalyst to catalyze the formation of the Si nanowires in high temperature tube furnace. The growth direction of the straight Si nanowires is <111> and the polyhedron η″-Cu₃Si alloy is on the tip of the Si nanowires. The synthesis temperature of the Si nanowires is 500 °C. Such a low temperature implies that the vapor-solid (VS) should be the growth method. The cheap Cu catalyst is favorable for the mass synthesis of Si nanowires.     

Origin of self-limiting oxidation of Si nanowires

A new kinetic model is suggested to describe the self-limiting oxidation of Si nanowires by only considering the diffusion step with the influence of stress due to the two-dimension nonuniform deformation of the oxide but not including any rate-limiting step for interfacial reaction. It is assumed the stress results in the change of distribution of diffusion activation energy in the high density region which rises monotonically along with the oxidation, and may be the main physical origin of the self-limiting oxidation behavior of SiNWs. Moreover, the present kinetic model can excellently describe the experimental results for the wide initial diameter over the range of self-limiting oxidation temperature.