Microthyristor-based sequential circuits and systems

This paper describes the construction of new circuit configurations for some sequential circuits. These circuits are based on the microthyristor as a microelectronic bistable device that can store logic one and logic zero and on NMOS transistors that act either as pass transistors or drivers. The shift register, considered as a main type of sequential circuit, is developed from a D flip-flop that is designed basically from the microthyristor as a bistable device. Moreover, different types of counters based on the microthyristor as a storing element are developed. Microthyristor sequential circuits were found to perform well.     

Proposal of dual-powered superconducting logic circuits

A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.     

CMOS触发器的一种传输函数分析法

触发器是构成时序逻辑电路的存储单元和核心部件。利用开关级设计的CMOS传输函数理论和信号流图,讨论了CMOS主从D触发器的工作原理;提出了CMOS触发器的一种传输函数分析法,并给出了应用实例。可以看出,这种方法对于CMOS触发器电路分析和设计是有效且方便的。     

基于1-of-2共振隧穿数据选择器的可置位复位D触发器设计

文章以共振隧穿RT器件为主要器件,设计了上边沿触发的共振隧穿D触发器.该触发器以1-of-2共振隧穿数据选择器为核心电路,带预先置位和复位功能.此共振隧穿数据选择器电路的设计方法还能用于实现其他触发器电路,为采用基于RT器件设计触发器电路提供了一种新的并且有效简单的方法,弥补了共振隧穿电路中只能用MOBILE单元来设计时序电路的单一性,丰富了量子电路中触发器的类型.     

RSYN: a system for automated synthesis of reliable multilevelcircuits

Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN     

Redundancies and don't cares in sequential logic synthesis

The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions.In this article, we explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense, but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty State Transition Graph (STG) that is equivalent to the STG of the true machine.We present a classification of redundant faults in sequential circuits composed of single or interacting finite state machines. For each of the different classes of redundancies, we define don't care sets which if optimally exploited will result in the implicit elimination of any such redundancies in a given circuit. We present systematic methods for the exploitation of sequential don't cares that correspond to sequences of vectors that never appear in cascaded or interacting sequential circuits. Using these don't care sets in an optimal sequential synthesis procedure of state minimization, state assignment, and combinational logic optimization results in fully testable lumped or interacting finite state machines. We present experimental results which indicate that medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times by exploiting these don't cares.     

Flip-flop circuit using a resonant-tunnelling hot electron transistor (RHET)

The letter proposes a flip-flop circuit using a resonant-tunnelling hot electron transistor (RHET). The circuit uses a resistor in series with the base of the RHET to make bistable states. Preliminary tests have demonstrated that the circuit can be used as a static memory element, indicating that the RHET has a superior potential for use in memory and/or logic circuits.     

触发器可靠度计算的F-PTM方法

传统的概率转移矩阵（PTM）方法是一种用于估计软错误对组合电路可靠度影响的有效方法,但传统PTM方法只适用于组合逻辑电路的可靠度评估.触发器是时序逻辑电路的重要组成部分,其可靠度评估对时序电路的可靠度分析研究至关重要.为此,本文提出了基于PTM的触发器可靠度计算的F-PTM方法及电路PTM的判定定理.F-PTM方法首先建立触发器电路的特征方程,再用电路PTM的判定定理生成触发器的PTM,最后,根据输入信号的概率分布函数计算出电路的可靠度.与传统PTM方法相比较,F-PTM方法既能计算组合电路的PTM,又能计算触发器电路的PTM,其通用性强.对典型的触发器电路和74X系列电路中的触发器电路的实验结果表明,F-PTM方法合理可行.与多阶段方法和Monte Carlo方法的实验结果相比较,F-PTM方法得到的结果更精确.     

Design of sequential circuits by quantum-dot cellular automata

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switching of this technology. The characterization of a D-type FF as a device consisting of an embedded wire is also presented. Unique timing constraints in QCA sequential logic design are identified and investigated. An algorithm for assigning appropriate clocking zones to a QCA sequential circuit is proposed. A technique referred to as stretching is used in the algorithm to ensure timing and delay matching. This algorithm relies on a topological sorting and enumeration step to consistently traversing only once the edges of the graph representation of the QCA sequential circuit. Examples of QCA sequential circuits are provided.     

An integrated JK flip-flop circuit

An integrated JK flip-flop circuit, which is constructed using an RS flip-flop and four gates, is described. The circuit operation is based on an original concept, which is different from the conventional master-slave principle. Results of a monolithic integration using emitter-coupled logic (ECL) circuits are also given. As compared with the conventional master-slave-type JK flip-flop, which is constructed using ECL, a 40 percent improvement in speed-power product has been obtained.     

基于形状工程的可靠磁性逻辑器件和触发器实现

纳米级磁性逻辑器件是一种新兴的场耦合计算范例,可用于实现非易失性和极低功耗的磁性逻辑电路.然而,杂散磁场和温度波动热效应阻碍了器件和电路的可靠转换.该文研究了对称缺失等腰三角形特殊形状纳磁体的转换特性,提出了利用这种特殊形状纳磁体实现磁性逻辑器件可靠转换的方法.基于特殊形状纳磁体器件设计了流水线RS触发器时序电路,并采用OOMMF软件进行了性能模拟.结果表明,特殊形状纳磁体实现的基本触发器电路不但能够进行可靠的流水线计算,同时还具有较高的工作温度和良好的按比例缩小特征.     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%.     

绝热电路稳定性和三时钟绝热同步时序电路

因为稳定性对绝热同步时序电路实现的重要性，该文首先提出绝热记忆电路的稳定性条件。依据稳定性条件，该文证明三相时钟是满足电路稳定性的最小值。在此基础上该文又提出三相时钟绝热动静态触发器，用此触发器设计出带有反馈清0的绝热可变计数电路。最后用计算机模拟程序检验绝热触发器和可变计数电路的结果。     

Synthesis methodology for magnetic domain wall logic

The demonstration of NOT and OR logic gates using magnetic domain walls could suggest that digital circuit design methodology may apply directly to this new technology to build complex circuits. This paper shows that the use of an external rotating field which propagates domain walls of opposite magnetization in antiphase instants, reveals unforeseen delays which modify the operation of sequential logic circuits. To overcome this difficulty and to introduce a design methodology, a new device capable of re-synchronizing the signals is presented.     

基于2N-2N2P结构的绝热非整数除电路设计

该文首先利用2N-2N2P逻辑电路结构,实现能量和信息均可恢复的绝热触发器,然后利用误差计算和偏差校正的方法,提出稳定的能量信息恢复型绝热非整数除电路设计方案,最后用计算机模拟程序检验了上述电路的正确性。     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

Synthesis for logical initializability of synchronous finite-statemachines

Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, X) simulator. In practice, commercial logic and fault simulators often require initialization under such a three-valued simulation model. In this paper, the first sound and systematic synthesis method is proposed to ensure the logical initializability of synchronous finite-state machines. The method includes both state assignment and combinational logic synthesis steps. It is shown that a previous approach to synthesis-for-initializability, which uses a constrained state assignment method, may produce uninitializable circuits. Here, a new state assignment method is proposed that is guaranteed correct. Furthermore, it is shown that combinational logic synthesis also has a direct impact on initializability; necessary and sufficient constraints on combinational logic synthesis are proposed to guarantee that the resulting gate-level circuits are logically initializable. The above two synthesis steps have been incorporated into a computer-aided design tool, SALSIFY, targeted to both two-level and multilevel implementations