SOI CMOS SRAM单元单粒子翻转效应的模拟

为简单快速模拟静态随机存储器(SRAM)的单粒子效应,在二维器件数值模拟的基础上,以经典的双指数模型为原型,通过数值拟合得到了单粒子效应瞬态电流脉冲的表达式,考虑晶体管偏压对瞬态电流的影响,得到修正的瞬态电流表达式,将其带入电路模拟软件HSPICE中进行SRAM存储单元单粒子翻转效应的电路模拟,通过与实际单粒子实验结果的对比,验证了这种模拟方法的实用性。     

用SOI技术提高CMOS SRAM的抗单粒子翻转能力

提高静态随机存储器（SRAM）的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅（SOI）基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61．8MeV／（mg／cm^2）,优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。     

PMOS晶体管工艺参数变化对SRAM单元翻转恢复效应影响的研究

基于Synopsys公司3D TCAD器件模拟,该文通过改变3种工艺参数,研究65 nm体硅CMOS工艺下PMOS晶体管工艺参数变化对静态随机存储器(Static Random Access Memory, SRAM)存储单元翻转恢复效应的影响。研究结果表明：降低PMOS晶体管的P+深阱掺杂浓度、N阱掺杂浓度或调阈掺杂浓度,有助于减小翻转恢复所需的线性能量传输值(Linear Energy Transfer, LET);通过降低PMOS晶体管的P+深阱掺杂浓度和N阱掺杂浓度,使翻转恢复时间变长。该文研究结论有助于优化SRAM存储单元抗单粒子效应(Single-Event Effect, SEE)设计,并且可以指导体硅CMOS工艺下抗辐射集成电路的研究。     

抗单粒子翻转效应的SRAM研究与设计

在空间应用和核辐射环境中,单粒子翻转(SEU)效应严重影响SRAM的可靠性。采用错误检测与校正(EDAC)和版图设计加固技术研究和设计了一款抗辐射SRAM芯片,以提高SRAM的抗单粒子翻转效应能力。内置的EDAC模块不仅实现了对存储数据"纠一检二"的功能,其附加的存储数据错误标志位还简化了SRAM的测试方案。通过SRAM原型芯片的流片和测试,验证了EDAC电路的功能。与三模冗余技术相比,所设计的抗辐射SRAM芯片具有面积小、集成度高以及低功耗等优点。     

静态存储器中子单粒子翻转截面的预测模型

中子是近地空间和核爆的主要辐射源之一,中子二次反应诱发的单粒子效应极大地影响了电子元器件的可靠性。本文针对商用体硅工艺静态存储器(SRAM)单元提出了一种中子饱和翻转截面预测模型。通过一个电路级的仿真模型,对应于辐射作用距离的线性电荷沉积(LET)效应可以通过基于SPICE仿真曲线来表现,进而用来预测翻转截面。该方法简单有效,预测结果与130 nm体硅工艺的中子实验结果吻合。     

温度对SRAM器件单粒子翻转重离子测试的影响

本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上（HIRLF）研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。     

基于TSV转接板的3D SRAM单粒子多位翻转效应

为了研究硅通孔(TSV)转接板及重离子种类和能量对3D静态随机存储器(SRAM)单粒子多位翻转(MBU)效应的影响,建立了基于TSV转接板的2层堆叠3D封装SRAM模型,并选取6组相同线性能量传递(LET)值、不同能量的离子(¹¹B与^4He、²⁸Si与¹⁹F、⁵⁸Ni与²⁷Si、⁸⁶Kr与⁴⁰Ca、¹⁰⁷Ag与⁷⁴Ge、¹⁸¹Ta与¹³²Xe)进行蒙特卡洛仿真。结果表明,对于2层堆叠的TSV 3D封装SRAM,低能离子入射时,在Si路径下,下堆叠层SRAM多位翻转率比上堆叠层高,在TSV(Cu)路径下,下堆叠层SRAM多位翻转率比Si路径下更大;具有相同LET值的高能离子产生的影响较小。相比2D SRAM,在空间辐射环境中使用基于TSV转接板技术的3D封装SRAM时,需要进行更严格的评估。     

基于SRAM软错误失效概率的交织距离选择模型

在静态存储器(SRAM)抗辐射加固设计中,单错误纠错码(SEC)联合交织是解决空间SRAM多比特翻转(MBU)的有效方法。交织距离(ID)的选择应当使MBU分布在不同的物理字中,ID越大,电路实现越复杂,功耗和面积也越大。基于SRAM在空间产生的MBU错误图样以及数目,在已有的ID选择模型上进行修正,提出了一种精确的评估模型。     

不同规模SRAM辐射损伤效应的研究

通过对ETC公司的商用256 kb和1 Mb CMOS SRAM器件在不同偏置条件(包括静态偏置和动态读写偏置)下进行电离辐射效应的研究,获得了SRAM器件电气参数和功能出错数随总剂量的响应关系.实验结果表明,功耗电流随累积剂量的增加变化明显,可以作为表征SRAM辐射损伤的敏感参数,但功能出错数与功耗电流的变化不同步,与功耗电流没有必然联系,原因是功能出错主要由栅氧阈值电压负漂引起,而功耗电流的增加主要由栅氧和场氧阈值电压负漂造成的漏电引起.     

Evaluation of resistance of CMOS LSIC to the factor of absorbed dose under the pulsed radiation effect

A method of testing CMOS VLSIs for resistance to the factor of the absorbed dose under the effect of high-intense pulsed ionizing radiation by the results of analysis of the reaction of the LSIC in the radiation field of a sequence of relatively low-intense pulses is suggested and substantiated. The approach makes it possible to evaluate the levels of radiation resistance of CMOS LSICs at small simulating installations under the dose gained in the mode of a series of pulses. Conservatism is provided with respect to charge transfer and relaxation in the oxide of MOS structures being independent of the field mode and sample topology.     

Single event upset and total dose radiation effects on rad-hard SRAMs

Radiation hardened 16K and 64K CMOS SRAMs were tested at the Brookhaven SEU Test Facility. No failures of 16K SRAMs were observed at room temperature with any value of the feedback resistors. SEU cross section measured at elevated temperatures was a function of reduced feedback resistance. A difference was observed in critical LET forBr andAu ions. SEU cross section decreased at very high angles of incidence. After initial SEU testing, the 64K SRAM was degraded by proton total dose irradiation. An increase in the SEU cross section as well as imprinting of the memory pattern was observed. Test chips fabricated by the same technology were also submitted to proton radiation. Threshold voltage shift was measured for NMOS transistors with and without inversion bias. An increase in the density of interface states for both NMOS and PMOS transistors was measured by the charge-pumping technique. This research has been supported by the NASA grants NAG-5-929 and NAG-9-333.     

The effect of neutron radiation on the photoelectric parameters of ITO-GaSe structures

The effect of 1-MeV neutrons on the photoelectric parameters of ITO-GaSe heterostructures was studied. It is shown that the observed variations in the current-voltage characteristics are caused by the effect of penetrating radiation on both components of the structure, which brings about an increase in the resistance of the heterostructures. The presence of exciton fine structure in the photosensitivity spectra after irradiation indicates that GaSe retains high structural quality notwithstanding the introduced radiation defects. The results obtained are accounted for by spatial redistribution of doping impurity in GaSe and structural changes in the ITO films.     

Modeling neutron ionization effects on high-density CMOS circuit elements

The mechanisms are analyzed of the action of neutrons on high-density CMOS circuit elements. A procedure is proposed for calculating the single-event-upset and single-hard-error cross sections of CMOS memory cells exposed to neutrons.     

脉冲激光干扰面阵CCD成像系统的实验研究

为了研究脉冲激光对面阵CCD的干扰效果,采用近场模拟实验的方法,设计了重复频率脉冲激光干扰CCD成像器件近场实验。当CCD器件表面接收激光功率密度达到2.97mJ/cm2时,观察和记录了CCD器件串音饱和现象;当CCD摄像机电子快门打开时,除发射窗口有激光光斑图像外,激光脉冲在激光器出光口竖直方向也会形成偏离出光口位置的漂移光斑图像。分析了CCD摄像机电子快门作用机理及图像信号转移方式机理,并对光斑漂移现象给出了合理解释。结果表明,重复频率脉冲激光可使CCD图像上出现漂移光斑而对图像形成干扰。这为重频脉冲激光干扰CCD的研究提供了理论基础和初步实验验证。     

Radiation hardened design and analysis of radiation effect for scientific CMOS image sensor

A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to single-event latch up for LET up to110 MeV·cm²/mg.     

Degradation of integrated schmitt triggers of the CMOS logic under the effect of ultrashort pulsed overloads

Degradation of a Schmitt trigger of the CMOS logic under the effect of ultrashort electrical pulses (USPs) is studied. It is shown that narrowing of the uncertainty region for a Schmitt trigger occurs under the effect of USPs. The circuit of the trigger has been simulated with all possible breakdowns of the MOS transistor taken into consideration. An experimental setup making it possible to determine the critical parameters of the effect of USPs on integrated circuits of triggers and CMOS structures is described.     

Research on the effect of single-event transient of an on-chip linear voltage regulator fabricated on 130 nm commercial CMOS technology

We report single-event transient (SET) responses of an on-chip linear voltage regulator in 130 nm commercial standard CMOS technology by heavy ion experiments at first. Responses can be distinguished by the load current. When the light load current was applied, the negative SET on the output of the regulator larger than 200 mV was not observed, while the positive SETs that are larger than 400 mV and last for about 200 ns were observed. By comparison, when the heavy load current was applied, both positive and negative SETs that are larger than 400 mV and last for several hundred ns were observed. Next, the mechanism behind the phenomenon is analysed and then verified by the post-layout SPICE circuit simulation. It is demonstrated that the input voltage, load current and the load capacitance are key elements in determining the severity of SET. Finally, the most sensitive node is located by analysis and SPICE circuit simulation, which lies in the output of the amplifier inside of the bandgap reference (BGR). This result is a primary consideration in the development of the hardening technique.