A Novel High Performance Architecture for H.264/AVC Deblocking Filtering

This letter presents an architecture based on a new double‐filter strategy to perform the adaptive in‐loop filtering process specified by the H.264/AVC standard. The proposed architecture shows considerable advantages, both in terms of hardware cost and latency, when compared with the approaches found in the most recent literature.     

H.264中的去方块滤波

介绍了H.264视频编码标准中的自适应去方块滤波的原理、过程及参数选取,并在此基础上进行了仿真实验。实验结果表明,去方块滤波在提高图像质量和降低编码视频码率上效果显著。     

Configurable VLSI Architecture for Deblocking Filter in H.264/AVC

In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a configurable, extensible, and synthesizable window-based processing architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the memory performance of the proposed architecture is improved by four times when compared to previous designs. Moreover, the system performance of our window-based architecture significantly outperforms the previous designs from 7 times to 20 times.     

H.264去块滤波快速算法的设计与实现

介绍了H.264去块滤波的基本原理,并基于滤波强度预判的思想提出了一种快速去块滤波算法.通过软件实现验证了该算法在不影响解码图像质量的前提下较标准中的算法节省了约70%的滤波运算量,有效提高了软件解码器的运行速度,有助于H.264解码器实时应用的实现.     

A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder

We propose a high-performance hardwired deblocking filter for H.264/AVC decoding. To decode QFHD (3840 $times$ 2160, i.e., four times full HD) ultra high definition video, we minimize number of processing cycles, working frequency and amount of external memory traffic. We propose a novel filtering order and employ a 5-stage pipelined and resource-shared dual-edge filter to generate two filtering results every cycle. Taking advantage of skip modes, our filter takes only 48 cycles to filter a macroblock in the best case and 100 in the worst case. Furthermore, it eliminates most unnecessary off-chip memory traffic with a novel on-chip memory scheme. Our design can support QFHD at 30 fps application by running only at 98 MHz.      

H.264/AVC中去块效应滤波系统的结构设计

针对H.264/AVC解码器中的去块效应滤波系统提出了一种有效的VLSI硬件结构.该系统是基于OR1200处理器挂于Wishbone总线上,采用UMC0.18 CMOS工艺流片.该系统较以往去块效应滤波系统具有高效率低复杂度等特点.由仿真综合结果可知,该系统在工作频率100MHz时对HDTV(1 920×1 088@29 fps;1 280×720@66 fps)能较好实现实时滤波,并且综合后的逻辑门只有15.33 k(不含片内SRAM).     

A Very High Throughput Deblocking Filter for H.264/AVC

This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) and a dedicated data arrangement in local memory banks, the proposed architecture can process filtering operations for one macroblock with less filtering cycles than previously proposed approaches. Whereas, filtering efficiency is improved due to a novel computation scheduling and a dedicated architecture composed of six filtering cores. It can be used either into the decoder or the encoder as a hardware accelerator for the processor or can be embedded into a full-hardware codec. This developed Intellectual Property block-based on the proposed architecture supports multiple and high definition processing flows in real time. While working at clock frequency of 150 MHz, synthesized under 65 nm low power and low voltage CMOS standard cell technology, it easily meets the throughput requirements for 4 k video at 30 fps of all the levels in H.264/AVC video coding standard and consumes 25.08 Kgates.     

H.264解码器中一种新颖的去块效应滤波器设计

在此完成了H.264/AVC解码器中高效低功耗的去块效应滤波器设计.该设计采用5阶流水线技术,配合混合边界滤波顺序与打乱次序的存储数据更新机制,解决了数据与结构冒险问题,因此获得了正常流水线操作中的0延迟,使得基于流水线的设计架构得到最大程度的实现,同时提高了系统吞吐量并降低了功耗.该设计在FPGA芯片上验证的工作频率上限大约为200 MHz,吞吐量为滤波单个宏块需要198个时钟周期.使用0.18μmCMOS工艺,Synopsys Co.的DC工具对滤波器模块进行综合,结果为时序收敛,功耗约为2μW.仿真结果显示,可以对QCIF标准的视频(60 f/s)进行实时环路滤波,该环路滤波器可以用于H.264/Avc实时解码器中.     

H.264/AVC中去块效应环路滤波的VLSI实现

提出了一种适用于H.264编解码环内去块效应滤波的VLSI结构。利用相邻4×4像素块间数据的依赖关系合理组织数据存储顺序,并通过增加本地SRAM,使垂直滤波数据来自本地,读写外部SDRAM的次数减半,从而大大减少滤波处理的周期数。设置转置寄存器,水平滤波和垂直滤波可共用一维滤波电路。仿真结果显示,一个宏块去块效应滤波仅需要230个周期。在0.18μm工艺下,最大频率100M时,综合逻辑门数为14K。     

AVS环路滤波专用结构

提出了一种用于AVS去块效应虑波的实用环路滤波结构.使用优化的滤波顺序,处理一个宏块只需要168个周期,而且硬件面积大大减小.实验表明,使用0.18μm CMOS工艺,所提出的结构只需要11.23千门.在50 MHz工作频率下,能够支持AVS高清视频解码的实时滤波处理.     

无SRAM的H.264/AVC去块效应滤波器

针对H.264/AVC中的去块效应滤波器,该文提出了一种新的滤波处理顺序,能够显著减小片上数据缓存容量,并以此为基础设计了一种去块效应滤波器的VLSI硬件新结构。该结构利用数据复用机制减少对片外存储的访问量、节省处理时间,同时不使用片内SRAM,将对片内SRAM的访问降为0。仿真结果显示,该电路在工作频率为100MHz时对HDTV能较好地实现实时滤波;在0.18m工艺下,综合后的等效逻辑门数只有16.8k。     

Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction‐level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.     

A Fast Architecture for H.264/AVC Deblocking Filter Using a Clock Cycles Saving Process

In this paper a fast architecture for Deblocking Filter in H.264/AVC video coding standard is presented. This architecture consists of a jump circuit which can increase the processing speed. To reduce the system complexity, we consider a single port external memory to be connected to our architecture which is designed with the minimum hardware cost compared to other kinds of architecture. Accessing to the external memory is reduced by reusing stored blocks. Filtering operation is concurrent with reading/writing blocks. Simulation results show that the processing cycle count of the proposed architecture has decreased comparing to other similar architectures.     

H.264去块滤波算法及硬件实现

H.264是ITU-T/ISO在2003年公布的最新的国际视频压缩编码标准,它大大提高了编码效率和图像质量,其中一个重要原因是在编解码环路中引入了去块滤波器。介绍了H.264视频编码标准中的去块滤波算法,并提出了一种可实现的去块滤波器硬件结构。该结构通过合理利用本地SRAM资源,大大减少了总线带宽需求,提高了硬件处理速度。仿真结果显示,通过该去块滤波器进行环路滤波,很大程度地消除了方块效应,图像质量得到明显改善。     

A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications

This work presents an efficient architecture design for deblocking filter in H.264/AVC using a novel fast-deblocking boundary-strength (FDBS) technique. Based on the FDBS technique, the proposed architecture divides the deblocking process into three filtering modes, namely offset-based, standard-based and diagonal-based filtering modes, to reduce the blocking artifact and improve the video quality in H.264/AVC. The proposed architecture is designed in Verilog HDL, simulated with Quartus II and synthesized using 0.18 μm CMOS cells library with the Synopsys Design Compiler. Simulation results demonstrate good performance in PSNR improvement and bit-rate reduction. Additionally, verification results through physical chip design reveal that the proposed architecture design can support 1,280 × 720@30 Hz processing throughput while clocking at 100 MHz. Comparisons with other studies show the excellent properties of the proposed architecture in terms of gate count, memory size and clock-cycle/macroblock.

H.264视频编解码器中去方块滤波的实现

基于块的混合编码是H.261、H.263、H.264、JPEG、MPEG的基本编码方案,然而在量化系数较大的情况下会产生明显的方块效应.对于图像中的平滑区域,我们的方法利用了同一块中原始像素的连续性以及相邻块的相关性等特征来减小跨边界像素点的不连续性.对于边缘区域,采用了一个边缘保留平滑滤波器.实验结果表明,该去方块滤波器在平滑噪声和消去方块效应的同时,能保留图像的主要结构特征,在提高图像主观质量和降低编码视频码率上效果显著。     

H．264/AVC解码器中去块效应滤波系统

本文介绍了H．264/AVC编解码器中块效应产生的原因及去块效应滤波的算法原理,提出了基于FPGA平台实现的H．264/AVC解码器中的去块效应滤波系统的硬件设计方法,并通过了仿真验证。     

基于CUDA的H.264去方块滤波的设计与实现

详细分析了统一计算设备架构(CUDA)的编程模型,从并行计算角度对H.264视频编解码中的去方块滤波进行研究和优化,提出了基于CUDA加速的去方块滤波并行处理方法.通过对高清测试序列的实验表明,利用GPU并行处理能力能够明显提高视频编解码速度,并有效降低CPU资源占用率.     

A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters

Deblocking filter is one of the most time consuming modules in the H.264/AVC decoder as indicated in many studies. Therefore, accelerating deblocking filter is critical for improving the overall decoding performance. This paper proposes a novel parallel algorithm for H.264/AVC deblocking filter to speed the H.264/AVC decoder up. We exploit pixel-level data parallelism among filtering steps, and observe that results of each filtering step only affect a limited region of pixels. We call this “the limited propagation effect”. Based on this observation, the proposed algorithm could partition a frame into multiple independent rectangles with arbitrary granularity. The proposed parallel deblocking filter algorithm requires very little synchronization overhead, and provides good scalability. Experimental results show that applying the proposed parallelization method to a SIMD optimized sequential deblocking filter achieves up to 95.31% and 224.07% speedup on a two-core and four-core processor, respectively. We have also observed a significant speedup for H.264/AVC decoding, 21% and 34% on a two-core and four-core processor, respectively.

H.264基本档次码流解析的专用处理器设计

针对解析H.264基本档次码流提出一种专用处理器的设计方案,它采用软/硬件联合设计的方法.使硬件电路解码模块可实现每个时钟周期从码流中解析出1个码字的处理速度,比采用树形结构的纯软件方案提高了50倍.