开关电阻对SC放大器速度的影响和优化方法

在开关电容(SC)放大器中,由于MOS开关导通电阻的存在,会对其建立速度产生影响.首先使用跨导运算放大器的一阶线性模型推导了包含开关导通电阻的开关电容放大器的闭环传输函数,通过分析极点和零点的分布,研究了放大器中不同位置开关的导通电阻对阶跃响应的影响.进而提出了一种MOS开关的优化设计方法来缩短放大器阶跃响应的建立时间.最后使用电路仿真工具验证了该方法的有效性.     

开关电容滤波器的电路与使用

一、概述模拟滤波器的小型化一直是各种通信系统发展中的一个重要问题。六十年代,低成本高性能单片运算放大器的发展,导致了以有源RC滤波器来代替无源RLC滤波器。但在硅片上制作电阻和电容元件时,其精确性及温度稳定性都比较差,因此RC有源滤波器难以用单片硅片实现。随着金属-氧化物半导体(MOS)集成电路技术的发展,近年来出现了MOS开关电容(SC)滤波器,它由MOS电路的开关、电容器和运算放大器构成。用时钟信号控制开关和电     

对寄生电容不灵敏的开关电容有源滤波器的设计

采用单位缓冲器设计对寄生电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件，利用该元件对椭圆函数式LC低通滤波器进行SC模拟。为了获得电容最佳值，提出了一种简单的最优化方法；并采用寄生电阻预畸变与SC负电阻相结合的办法，设计的SC滤波器对寄生电容不灵敏，且电路简单。在电子工作平台(EWB)上进行五阶椭圆低通SC-FDNR滤波器仿真，测量数据最大相对误差为0．948％，仿真结果表明该方法实用可行，效果明显。     

对寄生电容不灵敏的开关电容有源FDNR滤波器的设计

采用单位缓冲器设计对寄生电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件，利用该元件对椭园函数式LC低通滤波器进行SC模拟。为了获得电容最佳值，提出了一种简单的最优化方法；并采用寄生电阻预畸变与SC负电阻相结合的办法，设计的SC滤波器对寄生电容不灵敏，且电路简单。在电子工作平台(EWB)上进行五阶椭园低通SC-FDNR滤波器仿真，测量数据最大相对误差为0．948％，仿真结果表明该方法实用可行，效果明显。     

采用有源电容倍增器改善开关电容DC-DC变换器的性能

研究了开关电容DC-DC变换器输出电压与电容的关系,分析了变换器输出电压波纹产生的原因.针对变换器中大电容难集成的问题,提出了一种基于跨导放大器和第二代电流传输器的有源电容倍增器的新型拓扑结构.该电路只用较少的元件就可以实现开关电容变换器中的浮地和接地电容.以二阶开关电容DC-DC变换器为例,用PSPICE软件分别对采用了有源电容倍增器的新型结构和传统结构进行了仿真.结果显示,基于有源电容倍增器的开关电容变换器仅用100pF电容就等效了200nF电容的输出性能,而且具有更低的输出电压波纹.     

寄生不灵敏的维纳最佳三阶SCP

本文根据维纳最佳条件,设计了三阶开关电容锁相(环Switched-Capacitor Phase-loched loops,SCP),并分析了它的一些主要特性。结果表明,经双线性变换映射后的维纳最佳环路滤波器,可用寄生不敏感的SC支路精确实现。由此构成的锁相环路,具有捕捉带宽只受时钟频率及压控振荡器上限频率的限制,与滤波器的时间常数无关。     

用于高频的新颖开关电容积分器

本文研究了用于开关电容(SC)滤波器的离散积分器,所推荐的积分器是由无耗离散积分器(LDI)和双线性离散积分器的最佳线性结合而成,因此,称之为组合离散积分器(CDI)。由于这个积分器使正常转折频率增加一倍,并使高频离散积分器误差减少到最低限度,所以它对高频应用是理想的。文中给出了组合离散积分器的几种SC实现,并且还给出了以组合离散积分器为基础,模拟一般一阶和二阶的模拟滤波器单元的SC电路。     

新型超级结MOSFET器件在PFC应用中的优势

超级结(Super-Junction)MOSFET器件基于电荷平衡技术,在减少导通电阻和寄生电容两方面提供了出色的性能,这通常需要折中权衡。有了较小的寄生电容,超级结MOSFET具有极快的开关特性并因此减少了开关损耗。自然地,这种快速开关特性伴有极高的dv/dt和di/dt,会通过器件和印刷电路板中的寄生元件而影响开关性能。特别地,对于在现代高频SMPS中使用的超级结MOSFET,很难抑制频率噪声     

开关电容网络及其应用

一、开关电容网络的构成和它产生的背景开关电容网络是由MOS电容、开关和运算放大器组成的集成化网络,简称SC网络。它是通过开关的动作和电容储存电荷的功能,在运算放大器的配合下,进行信号传递和处理的电路。这种电路能够完成多种模拟电路的功能,还能用MOS工艺与数字电路共片生产,组成单片模拟数字信号处理器件。它是电路向高精度、大规模集成化方向发展的产物。开关电容网络开始是为研究高精度、高密度集成滤波器而研制的,而后又被推广到其它     

简介《Analog MOS Integrated Circuits for Signal Processing》(信号处理的模拟MOS集成电路)一书

早在六十年代末就有使用开关和电容来构成滤波器的思想,到1977年随着MOS集成技术的发展,开关电容滤波器的研究工作才全面展开。这种由MOS电容、开关和运算放大器组成的网络(SC网络),具有高精度和高密度集成的特点,在国际上引起了广泛的重视。目前对开关电容网络的研究已扩展到非滤波方面的应用。我国许多高等院校及研究机构也有不少人从事这方面的研究工作。但有关SC网络的专门书籍目前还不多见。最近由JOHNWILEY & SONS公司出版的《Analog MOS Integrateol Circuits for Signal Processing》     

PARASITIC TOLERANT DIFFERENTIAL SC TRANSCONDUCTANCE USING UNITY GAIN BUFFERS

The unity gain buffer will be good to design high frequency SCF if its resistiveeffects can be eliminated,and therefore the whole parasitic sensitivities will greatly be reduced.On the basis of this concept,a novel parasitic tolerant SC DTE(differential transconductanceelement)is proposed.SC floating inductor and integrator fit for high frequency applications areformed by the DTE.The computer simulation and experiment on a third order elliptic LP filterverify its validity.     

Design techniques for high-frequency CMOS switched-capacitorfilters using non-op-amp-based unity-gain amplifiers

A fully differential non-op-amp-based unity-gain amplifier (UGA) is proposed, whose 3-dB frequency can be as high as 250 MHz in 3.5-μm p-well CMOS technology. The purpose is to develop a new design concept for high-frequency switched-capacitor (SC) filters which uses balanced non-op-amp type UGAs with tunable gain to replace conventional op-amp-based unity-gain buffers (UGBs). The proposed UGA has a normal gain of unit, but it has a greater bandwidth, better setting behavior, smaller chip area, and less transistors than op-amp-based UGB. The new UGA also has a fully differential balanced configuration. The balanced configuration and proper predistortion by CAD tools can reduce the error due to linear parasitic capacitances. Experimental results prove the capability of the proposed structures in the realization of high-frequency SC filters over the megahertz range     

New realization of inductances for switched-capacitor filters using voltage inverter switches

This paper describes a new design method of inductance simulation for switched-capacitor (SC) filters based on the VIS-SC concept. The resulting circuits have not only the excellent sensitivity behavior of VIS-SC filters, but also the low sensitivity to the main parasitics occuring in the MOS integrated circuit, i.e., the parasitic capacitances between the bottom plates of the implemented capacitors and substrate. As examples, a sixth-order band-pass and a sixth-order band-stop elliptic filter transformed from a third-order low-pass are given. Experimental results agree very well with theory. A brief analysis is given of certain parasitic effects in band-stop filters at the Nyquist frequency.     

SC filter circuit with decimation of sampling frequency

Realisation of a switched-capacitor filter circuit with decimation of the input sampling frequency is proposed. The circuit, which is compensated for the influence of parasitic capacitances, is useful as an input stage of an SC filter. It can also be used for the realisation of an integrator, based on Simpson's rule.     

Low-voltage and high-frequency Gm-opamp-C filter with automatic self frequency tuning

A 1.0 V, 10 MHz Gm-opamp-C filter is described. For low voltage and high frequency operation, the number of internal nodes is minimized to avoid the generation of parasitic poles and the number of stacked transistors between VDD and GND is limited to two. The frequency response of the filter is automatically tuned by a simple self tuning circuit. The measured dynamic range of the filter is 47 dB while dissipating 5 mA.     

应用于高Q跨导-电容带通滤波器的线性跨导运放设计

设计了一种具有高的直流增益的宽带线性全差分跨导运放.一方面,并联一个工作在线性区的场效应管来补偿直流三阶系数,得到了一种应用于连续时间滤波器、增加跨导器饱和区输入信号幅度的简单方法.另一方面,结合负电阻电路提高了输出阻抗,实现高的直流增益而不需要额外的内部结点,并减小了因有限直流增益和寄生电容引起的相位偏差.将此全差分跨导运放应用于0.18μmCMOS工艺二阶带通滤波器,在3.3V电源电压、输入峰峰值1V时,HSPICE仿真结果的总谐波失真小于40dB,中心频率为20MHz,3dB带宽为0.18MHz,即Q为110.     

Automatic Tuning System for Integrator-Based Continuous-Time Filters

This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system.     

A fully integrated switched-capacitor DC–DC converter with hybrid output regulation

In this paper, we propose a fully integrated switched-capacitor (SC) DC–DC converter with hybrid output regulation that allows a predictable switching noise spectrum. The proposed hybrid output regulation method is based on the digital capacitance modulation for fine regulation and the automatic frequency scaling for coarse regulation. The automatic frequency scaler and on-chip current sensor are implemented to adjust the switching frequency at one of the frequencies generated by a binary frequency divider with change in load current. Thus, the switching noise spectrum of the proposed SC DC–DC converter can be predicted over the entire load range. In addition, the bottom-plate losses due to the parasitic capacitances of the flying capacitors and the gate-drive losses due to the gate capacitances of switches are reduced at light load condition since the switching frequency is automatically adjusted. The proposed SC DC–DC converter was implemented in a 0.13 µm CMOS process with 1.5 V devices, and its measurement results show that the peak efficiency and the efficiency at light load condition are 69.2% and higher than 45%, respectively, while maintaining a predictable switching noise spectrum.