Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

New observation of gate current in off-state MOSFET

For a gate-controlled p⁺-n diode having gate-p⁺ overlap area of 3.7×10^-4 cm², the author reports a new observation of the leakage currents through a 235-Å gate oxide. The gate current components both due to Fowler-Nordheim electron funneling through the gate-p⁺ overlap oxide and due to hot-electron injections were separately detected. The corresponding gate current was found to be dominated by Fowler-Nordheim electron funneling prior to significant surface avalanche impact ionization     

Gate current and oxide reliability in p+ poly MOScapacitors with poly-Si and poly-Ge0.3Si0.7 gatematerial

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge_0.3Si_0.7 ) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φ_B, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q_bd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability     

Electrical characteristics of TiB2 for ULSI applications

The work function of TiB₂ was measured using Fowler-Nordheim tunneling in MOS capacitors, Schottky diode current measurements, capacitance-voltage techniques, and contact resistance. The resulting data place the Fermi level of TiB₂ about 0.9 eV below the silicon conduction band. Given this barrier height, Schottky diodes of TiB₂/p-Si exhibit ohmic characteristics, but the contact resistance of TiB₂ to n⁺ junctions is an order of magnitude higher than the generally desired value. Boron outdiffusion from TiB₂ into underlying silicon was observed at temperatures of 1000°C and greater. Boron diffusion from TiB₂ into silicon above 1000°C is enhanced compared to the conventionally accepted value of the boron diffusivity     

Effects of wafer temperature on plasma charging induced damage toMOS gate oxide

The effect of wafer temperature on damage to thin MOS gate oxide from plasma has been investigated for the first time. As the wafer surface temperature during an O₂ plasma exposure increases from 145°C to 340°C, the damage measured from charge-to-breakdown (Q_bd) increases dramatically. This result agrees with Fowler-Nordheim tunneling current mechanism for plasma charging and the temperature activated damage model. The increase of damage at higher wafer processing temperature indicates that elevated temperature plasma processes, such as plasma enhanced CVD and Cu etching, can be expected to be more susceptible to charging damage than low temperature plasma processes     

Full-Band Tunneling in High-κ Oxide MOS Structures

In this paper, we investigate the tunneling properties of ZrO₂ and HfO₂ high-k oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab-initio band dispersions. Transmission coefficients and tunneling currents have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with the same equivalent oxide thickness. The complex band structures of ZrO₂ and HfO₂ have been calculated and used to develop an energy-dependent effective tunneling mass model. We show that effective mass calculations based on this model yield tunneling currents in close agreement with full-band results.     

Drain-avalanche and hole-trapping induced gate leakage inthin-oxide MOS devices

Leakage current components due to band-to-band tunneling and avalanche breakdown in thin-oxide (90-160 Å) gated-diode structures are discussed. Experimental results show that while the band-to-band tunneling current is not sensitive to channel doping concentration, the avalanche current is sensitive to channel doping concentration in the range of 10¹⁶ to 10¹⁷ cm^-3. For oxides thicker than 110 Å, the gate current is found to be dominated by hot-hole injection and for oxides thinner than 110 Å the gate current is dominated by Fowler-Nordheim electron tunneling. After hot-hole injection, the gate oxide exhibits significant low-level leakage, which is explained by the barrier-lowering effect caused by the trapped holes in the oxide     

Optimized silicon-rich oxide (SRO) deposition process for 5 V onlyflash EEPROM applications

A process for depositing in-situ very-thin (<10 nm) SiO₂ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO₂ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm² at J=0.1 A/cm² . The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices     

Investigation of the Correlation Between Temperature and Enhancement of Electron Tunneling Current Through $hbox{HfO}_{bf 2}$ Gate Stacks

A model is established to describe the temperature dependence of the electron tunneling current through HfO₂ gate stacks based on analyzing the coupling between the longitudinal and transverse components of electron thermal energy caused by the difference of the effective electron mass between the HfO₂ gate stacks and silicon. By analyzing the three-dimensional Schrodinger equation for a MOS structure with HfO₂ gate stacks, a reduction in the barrier height is resulted from the large effective electron mass mismatch between the gate oxide and the gate (substrate). The calculated electron tunneling currents agree well with the experimental data over a wide temperature range. This coupling model can explain the temperature dependence of the electron tunneling current through HfO₂ gate stacks very well. The numerical results also demonstrate that the temperature dependence of the electron tunneling current strongly depends on the effective electron mass of HfO₂. This temperature sensitivity of the electron tunneling current can be proposed as a novel method to determine the effective electron mass of the gate oxide.     

Effect of physical stress on the degradation of thinSiO2 films under electrical stress

In this work, we demonstrate that for ultrathin MOS gate oxides, the reliability is closely related to the SiO₂/Si interfacial physical stress for constant current gate injection (V_g^- ) in the Fowler-Nordheim tunneling regime. A physical stress-enhanced bond-breaking model is proposed to explain this. The oxide breakdown mechanism is very closely related to the Si-Si bond formation from the breakage of Si-O-Si bond, and that is influenced by the physical stress in the film. The interfacial stress is generated due to the volume expansion from Si to SiO₂ during the thermal oxidation, and it is a strong function of growth conditions, such as temperature, growth rate, and growth ambient. Higher temperatures, lower oxidation rates, and higher steam concentrations allow faster stress relaxation through viscous flow. Reduced disorder at the interface results in better reliability. Fourier transform infrared spectroscopy (FTIR) technique has been used to characterize stress in thin oxide films grown by both furnace and rapid thermal process (RTP). In conjunction with the Gibbs free energy theory, this model successfully predicts the trends of time-to-breakdown (t_bd) as a function of oxide thickness and growth conditions. The trends of predicted t_bd values agree well with the experimental data from the electrical measurement     

Different dependence of band-to-band and Fowler-Nordheim tunnelingon source doping concentration of an n-MOSFET

As the value of the maximum source doping concentration in the gate/source overlap area of an n-channel MOSFET (N_dmax) varies, it has been observed that the edge Fowler-Nordheim (FN) tunneling through the gate oxide in the overlap area is changed significantly. In contrast, the N_dmax variation has little impact on band-to-band tunneling current (I_BB) induced in the same overlap area. We attribute the independence of I_BB on N _dmax to the inhibition of band-to-band tunneling at the N_dmax location where silicon band bending becomes less than 1.1 eV resulting from increase of source doping concentration N_d beyond ~1.6×10¹⁹ cm^-3 (this value depends on the device used and its bias condition)     

Gate current injection initiated by electron band-to-band tunnelingin MOS devices

A substrate hot-electron injection across the gate oxide initiated by electron band-to-band tunneling in p-type silicon is discussed. The injection electrons are generated by the energetic holes which are originally left behind by the band-to-band tunneling electrons. The injection can be easily controlled by an appropriate bias to a nearby n ⁺ diffusion, and the injection efficiency can be as high as 10^-2. Due to the small oxide field during injection, the electron fluence through the oxide before failure is much higher than under a Fowler-Nordheim tunneling stressing. These advantages make this band-to-band tunneling induced substrate hot-electron injection a possible programming mechanism for nonvolatile memories     

An operational definition for breakdown of thin thermal oxides of silicon

As MOS devices with thinner gate oxides are put into production, the high-field oxide breakdown definition used for process monitoring must be revised to account for noncatastrophic electrical conduction. This conduction is due to electron injection by Fowler-Nordheim tunneling into the oxide conduction band, and it can be as large as 0.1 A/cm²without causing irreversible breakdown of thin oxides. We propose that breakdown should be defined as the passage of a large current at a low value of applied electric field, after stressing of the oxide at a high field. We show that this definition represents a truly irreversible catastrophic breakdown, that it can be adapted easily for automated testing, and that it yields reliable results for breakdown of thin (less than 500 Å) gate oxides.     

Impact of gate direct tunneling current on circuit performance: asimulation study

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm⩽t_ox⩽1.5 nm, L_g=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V_dd static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices     

6H－SiC MOS结构电特性及其辐照效应的研究

对SiC MOS结构辐照引起的电参数退化及其电特性进行了研究。结果说明:在氧化层电场较高时Fowler-Nordheim隧穿电流决定着SiC MOS结构的漏电流,当幅照栅偏压为高的正电压时,电离幅照对SiC MOS电容的影响会更明显,SiC MOS器件比Si器件具有好的抗辐照的能力,在58kGy(Si)的辐照剂量下,其平带电压漂移不超过2V。     

A 1-Kbit EEPROM in SIMOX technology for high-temperatureapplications up to 250°C

A 1-Kbit high-temperature EEPROM memory module has been developed in a 1.6-μm thin-film SIMOX technology. The memory array is based on single-poly EEPROM cells, which are erased and programmed by Fowler-Nordheim tunneling. Operation at elevated temperatures is achieved by a special array design, suitable for elimination of cell-disturb problems caused by temperature-induced leakage currents of the select transistors. High-voltage switching is done without PMOS transistors in order to avoid leakage currents due to the backgate effect. The memory module is designed for 5-V only operation and offers an access time of 260 ns at an operating temperature of 250°C. At 250°C, data retention of 3000 h and an endurance of 10000 erase/program cycles has been achieved. The area of the 1-Kbit memory module is 0.89×2.71 mm²     

Stress-induced leakage current in p+ poly MOS capacitorswith poly-Si and poly-Si0.7Ge0.3 gatematerial

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si_0.7 Ge_0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices     

A novel photodetector using MOS tunneling structures

A metal/oxide/p-Si structure with ultrathin oxide is utilized as a photodetector. At positive gate bias, the dark current of the photodetector is limited by the thermal generation of minority carriers in the inversion layer. The high growth temperature (1000°C) of the gate oxide can reduce the dark current to a level as low as 3 nA/cm². As biased in the inversion layer, the tunneling diode works in the deep depletion region with soft pinning of oxide voltage, instead of the pinning of surface potential, very different from the conventional MOS diode with thick oxide     

Self-consistent modeling of resonant interband tunneling in bipolartunneling field-effect transistors

We present a model for the calculation of the tunneling current in resonant interband tunneling devices based on a transfer-Hamiltonian formalism. The model is fully self-consistent and includes electrons and both light and heavy holes. In particular, we show the viability of the bipolar tunneling field-effect transistor as a three-terminal multiple-NDR device with predicted currents reaching over 1000 A/cm² and theoretical peak-to-valley ratios up to 300