共查询到20条相似文献,搜索用时 78 毫秒
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H.264是ITU-T/ISO在2003年公布的最新的国际视频压缩编码标准,它大大提高了编码效率和图像质量,其中一个重要原因是在编解码环路中引入了去块滤波器。介绍了H.264视频编码标准中的去块滤波算法,并提出了一种可实现的去块滤波器硬件结构。该结构通过合理利用本地SRAM资源,大大减少了总线带宽需求,提高了硬件处理速度。仿真结果显示,通过该去块滤波器进行环路滤波,很大程度地消除了方块效应,图像质量得到明显改善。 相似文献
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H.265继续沿用H.264编码架构,去方块滤波器也是H.265视频编码标准的一个重要选项,去除混合编码带来的块效应极大改善了视频的质量,但由于H.265超级宏块的存在,去方块效应滤波相关参数层层嵌入在每个小的处理单元中,这种结构不利于实现基于宏块行间的并行化,同时也很难高效地利用Cortex-A9架构SIMD优化性能.首先详细分析H.265标准去块滤波器的处理过程以及并行处理的困难,进而提出一种便于实现基于宏块行间的并行去块滤波结构,然后进行Cortex-A9汇编优化.基于HM14.0实验,改进去方块效应滤波器计算复杂度从占整个解码器25%降至14%,大大提升了解码器性能,为移动设备上实现H.265大分辨率视频实时播放奠定基础. 相似文献
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提出了一种适用于H.264解码器环内去块滤波效应的ASIC结构.该结构利用两个滤波器完成滤波操作,大大减少了滤波处理的周期数(124).同时利用数据间的相关依赖性合理地安排滤波顺序.通过增加SRAM使左边相邻宏块和上边相邻宏块来自本地,减少外部SDRAM的读取次数.同时内置一个32×32bit暂置向量寄存器,完成水平滤波与垂直滤波的交替,使数据流入处理完成后按正确格式送出,减少数据重复读取. 相似文献
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在此完成了H.264/AVC解码器中高效低功耗的去块效应滤波器设计.该设计采用5阶流水线技术,配合混合边界滤波顺序与打乱次序的存储数据更新机制,解决了数据与结构冒险问题,因此获得了正常流水线操作中的0延迟,使得基于流水线的设计架构得到最大程度的实现,同时提高了系统吞吐量并降低了功耗.该设计在FPGA芯片上验证的工作频率上限大约为200 MHz,吞吐量为滤波单个宏块需要198个时钟周期.使用0.18μmCMOS工艺,Synopsys Co.的DC工具对滤波器模块进行综合,结果为时序收敛,功耗约为2μW.仿真结果显示,可以对QCIF标准的视频(60 f/s)进行实时环路滤波,该环路滤波器可以用于H.264/Avc实时解码器中. 相似文献
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本文提出基于GPU加速的图像及视频的实时抽象化绘制算法。首先通过运用Kuwahara滤波实现图像的颜色特征快速聚类,其次采用各向异性双边滤波算法对图像沿结构张量场进行平滑,从而获得连续的、局部区域色彩一致的结果图像,实验表明该算法简单、易于实现。 相似文献
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《Solid-State Circuits, IEEE Journal of》1986,21(6):956-963
New video transmission systems such as the satellite D2-MAC/packet system and second-generation local area networks for video-communications will use digital coding and decoding of video signals. To develop reliable and low-cost receivers, it appears necessary to implement the main functions using CMOS technology. Therefore many analog functions must be replaced by the equivalent digital ones before implementation. Digital circuits are described for the final video postprocessing, i.e. video postfiltering and dematrixing. An NMOS digital filter for Y, CR, and CB oversampling is presented. R, G, and B components are obtained using a CMOS matrix operator, also described. These two circuits are used in a 108-Mb/s experimental video decoder. 相似文献
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Golla C. Nava F. Cavallotti F. Cremonesi A. Casgrande G. 《Solid-State Circuits, IEEE Journal of》1990,25(6):1502-1509
A 30-MHz finite impulse response (FIR) programmable filter processor that has been developed using a 1.2-μm CMOS EPROM technology with single metal is discussed. Its 30-MHz worst-case operating frequency meets most video filtering requirements and demonstrates the potential of nonvolatile memory technologies in embedded applications. The processor has been designed with a high level of parallelism and pipelining by using a transposed FIR structure. In this approach, the multipliers are implemented with an EPROM-based look-up table containing the results of the products between video samples and filter coefficients, according to the user's application. The chap can implement every kind of FIR filter with a maximum complexity of 59 taps in a half-band filter configuration, 32 taps for a symmetric filter, and 167 taps for an asymmetric one. The equivalent coefficient precision is 12 b, assuming 8 b of input data precision. Multiprocessor configurations are allowed for more demanding performances such as longer filters, input signal precision extension, two-dimensional processing, and increased throughput 相似文献
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针对数字视频帧间平移抖动的稳定问题,介绍一种基于局部求精位平面匹配运动估计和约束卡尔曼滤波运动校正的视频稳定算法。运动估计首先结合了灰阶比特平面匹配和菱形搜索策略得到初步的估计结果,然后在其附近再以最小绝对差(MAD)为测度,搜索更为准确的运动估计结果。这种运动估计方法在保证估计精度的前提下,显著地减少了运动估计需要的计算量。运动校正则考虑到实际稳像系统对校正量可能存在的某些约束,对绝对帧位移曲线采用约束卡尔曼滤波,得到平滑的位移曲线,有效地降低了帧间抖动的幅度,同时保证了校正矢量不超过稳像系统的实际校正能力。仿真实验表明,该算法具有精度高、速度快的特点,尤其适用于实时视频稳定。 相似文献
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This correspondence deals with suboptimal multiplierless perfect reconstruction quadrature mirror filter (PR-QMF) solutions. It is shown that multiplierless PR-QMFs perform comparable to or better than the known filter banks and discrete-cosine-transform-based (DCT-based) image coding techniques objectively and subjectively. They are very efficient to implement on very large scale integrated (VLSI) systems. These PR-QMFs might find uses in real-time image and video coding and other applications 相似文献
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《Solid-State Circuits, IEEE Journal of》1983,18(3):280-285
Digital video signal processing is one result of the fast progress in NMOS-VLSI techniques. The attractions of using digital data processing methods in an analog application field are the availability of CAD tools for the design of digital ICs and the integration of digital filter functions. Besides the key components such as microcomputers, A/D, and D/A converters, the digital filter techniques are the most important functions in this application field. It is demonstrated that digital signal processing is not only restricted to amplitude modulated video signals, but also that frequency modulated signals can be processed and methods for FM modulation and demodulation have been developed. 相似文献
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HEVC in-loop deblocking filter significantly improves the subjective quality of coded video by removing blocking artifact. However, there are still visible blocking artifacts in the complex videos with fast and chaotic motions coded at a low bitrate. In this paper, we propose a three-step deblocking filter scheme, which pre-processes video to remove undesired noise, next removes the corner outliers, and then suppresses the normal blocking artifacts with adaptive deblocking filters. The whole deblocking filtering process is applied on both luma and chroma components. Experimental results show that the proposed method could effectively improve the subjective quality for various videos, and outperform other typical post-processing deblocking methods. 相似文献