Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

肖特基型β-Ga2O3日盲紫外光电探测器

本文制备并研究了肖特基型β-Ga₂O₃日盲紫外光电探测器.结果表明：通过脉冲激光沉积外延生长的β-Ga₂O₃的（-201）晶面 X射线衍射峰半高宽仅为36 arcsec,表现出了高的晶体质量;光暗条件下的I-V曲线显示所制备的器件具有明显的肖特基整流特性,在-5V偏压下暗电流保持在0.1nA量级,正向导通电压为1.5V;光电流谱显示器件在240nm处存在显著的峰值响应,并在260nm左右呈现陡峭的截止边,日盲紫外的带内带外抑制比达到1000.同时,也研究了不同掺杂对Ga₂O₃晶体质量的影响.     

磁控管用新型直热式稀土铪酸钆陶瓷阴极研究

为了提高大功率磁控管的输出功率,延长其使用寿命,采用难熔稀土氧化钆和过渡金属氧化铪制备大功率磁控管用新型直热式稀土铪酸钆陶瓷阴极,并对该阴极的热发射特性和寿命特性等进行了测试,热发射测试结果显示该阴极在1300℃ br即可提供0.1A/cm²发射电流密度,1600℃ br下可提供超过1.93A/cm²的发射电流密度.寿命实验结果显示,该阴极在1500℃ br,直流负载为0.5A/cm²的条件下,寿命已经超过4000h.最后,利用X射线衍射仪、扫描电镜、能谱分析仪、氩离子深度刻蚀俄歇电镜等设备分别对该阴极活性物质的分子结构,阴极表面微观形貌、元素成分及含量等进行了分析.结果表明,高温烧结合成了单一的铪酸钆物相,烧结过程中当一种Gd³⁺价稀土氧化钆掺入Hf⁴⁺价的过渡金属氧化铪时,会发生离子置换固溶,为了保持铪酸钆晶格的电中性,晶格中就会产生一个氧空位.当阴极在激活、老练、热发射测试时,会加速氧空位的生成,产生的氧空位越多,阴极表面导电性就会越好,这间接降低了逸出功,从而提高了阴极的热发射能力.     

Low Dit, thermodynamically stable Ga2O3-GaAs interfaces: fabrication, characterization, and modeling

Thermodynamically stable, low D_it amorphous Ga₂ O₃-(100) GaAs interfaces have been fabricated by extending molecular beam epitaxy (MBE) related techniques. We have investigated both in situ and ex situ Ga₂O₃ deposition schemes utilizing molecular beams of gallium oxide. The in situ technique employs Ga₂O₃ deposition on freshly grown, atomically ordered (100) GaAs epitaxial films in ultrahigh vacuum (UHV); the ex situ approach is based on thermal desorption of native GaAs oxides in UHV prior to Ga₂O₃ deposition. Unique electronic interface properties have been demonstrated for in situ fabricated Ga₂O₃-GaAs interfaces including a midgap interface state density D_it in the low 10¹⁰ cm^-2 eV^-1 range and an interface recombination velocity S of 4000 cm/s. The existence of strong inversion in both n- and p-type GaAs has been clearly established. We will also discuss the excellent thermodynamic and photochemical interface stability. Ex situ fabricated Ga₂O₃-GaAs interfaces are inferior but still of a high quality with S=9000 cm/s and a corresponding D_it in the upper 10¹⁰ cm^-2 eV^-1 range. We also developed a new numerical heterostructure model for the evaluation of capacitance-voltage (C-V), conductance-voltage (G-V), and photoluminescence (PL) data. The model involves selfconsistent interface analysis of electrical and optoelectronic measurement data and is tailored to the specifics of GaAs such as band-to-band luminescence and long minority carrier response time τ_R. We will further discuss equivalent circuits in strong inversion considering minority carrier generation using low-intensity light illumination     

Plasma-Enhanced Atomic Layer Deposition of Amorphous Ga2O3 for Solar-Blind Photodetection

Wide-bandgap gallium oxide(Ga₂O₃) is one of the most promising semiconductor materials for solar-blind(200 nm to 280 nm) photodetection. In its amorphous form, amorphous gallium oxide(a-Ga₂O₃) maintains its intrinsic optoelectronic properties while can be prepared at a low growth temperature, thus it is compatible with Si integrated circuits(ICs) technology. Herein, the a-Ga₂O₃ film is directly deposited on pre-fabricated Au inter...     

Effect of substrate temperature on the properties of deep ultraviolet transparent conductive ITO/Ga2O3 films

正ITO/Ga_2O_3 bi-layer films were deposited on quartz glass substrates by magnetron sputtering.The effect of substrate temperature on the structure,surface morphology,optical and electrical properties of ITO/Ga_2O_3 films was investigated by an X-ray diffractometer,a scanning electron microscope,a double beam spectrophotometer and the Hall system,respectively.The structural characteristics showed a dependence on substrate temperature. The resistivity of the films varied from 6.71×10~(-3) to 1.91×10~3Ω·cm as the substrate temperature increased from 100 to 350℃.ITO(22 nm)/Ga_2O_3(50 nm) films deposited at 300℃exhibited a low sheet resistance of 373.3Ω/□and high deep ultraviolet transmittance of 78.97%at the wavelength of 300 nm.     

Direct bonding between InP and rare earth iron garnet grown on Gd3Ga5O12 substrate by liquid phaseepitaxy

The bonding of InP and rare earth iron garnet grown on Gd₃ Ga₅O₁₂ substrate without any additional material demonstrated. After chemical treatment, heat treatment in H₂ ambient results in the bonding of the samples. This process is applicable to the integration of semiconductor and magneto-optic devices     

Transport properties of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors with Al2O3 of different thickness

The Al₂O₃ as a gate oxide and passivation was used to study the transport properties of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOSHFETs). Performance of the devices with Al₂O₃ of different thickness between 4 and 14 nm prepared by metal–organic chemical vapor deposition (MOCVD) and with 4 nm thick Al₂O₃ prepared by Al sputtering and oxidation was investigated. All MOS-devices yielded higher transconductance than their HFET counterparts, i.e. the transconductance/capacitance expected proportionality assuming the same carrier velocity was not fulfilled. A different electric field near/below the gate contact due to a reduction of traps is responsible for the carrier velocity enhancement in the channel of the MOSHFET. The trap reduction depends on the oxide used, as follows from the capacitance vs frequency dispersion for devices investigated. It is qualitatively in a good agreement with the different velocity enhancement evaluated, and devices with thinner oxide show higher traps reduction as well as higher transconductance enhancement. It is also shown that obtained conclusions can be applied well on performance of SiO₂/AlGaN/GaN MOSHFETs.     

Insulator passivation of In0.2Ga0.8As-GaAssurface quantum wells

The electronic passivation of (100) In_0.2Ga_0.8 As-GaAs surface quantum wells (QWs) using in situ deposition of an amorphous, insulating Ga₂O₃ film has been investigated and compared to standard Al_0.45Ga_0.55As passivation. Nonradiative lifetimes τ_r=1.1±0.2 and 1.2±0.2 ns have been inferred from the dependence of the internal quantum efficiency η on optical excitation density P₀' for the Ga₂O₃ and Al_0.45Ga_0.55As passivated In_0.02 Ga_0.8As-GaAs surface QW, respectively. Beyond identical internal quantum efficiency, the amorphous Ga₂O₃ insulator passivation simplifies device processing, eludes problems arising from lattice-mismatched interfaces, and virtually eliminates band bending in electronic and optoelectronic devices based on a low dimensional system such as quantum wells, wires, and dots     

Effects of Sc2O3 and MgO passivation layerson the output power of AlGaN/GaN HEMTs

The low temperature (100°C) deposition of Sc₂O₃ or MgO layers is found to significantly increase the output power of AlGaN/GaN HEMTs. At 4 GHz, there was a better than 3 dB increase in output power of 0.5×100 μm² HEMTs for both types of oxide passivation layers. Both Sc₂ O₃ and MgO produced larger output power increases at 4 GHz than conventional plasma-enhanced chemical vapor deposited (PECVD) SiN_x passivation which typically showed ⩽2 dB increase on the same types of devices. The HEMT gain also in general remained linear over a wider input power range with the Sc₂O₃ or MgO passivation. These films appear promising for reducing the effects of surface states on the DC and RF performance of AlGaN/GaN HEMTs     

Bi1.5Zn1.0 Nb1.5O7栅绝缘层的SiO2修饰对ZnO-TFTs性能的影响

具有高介电常数的栅绝缘层材料存在某种极化及耦合作用,使得ZnO-TFTs具有高的界面费米能级钉扎效应、大的电容耦合效应和低的载流子迁移率.为了解决这些问题,本文提出了一种使用SiO₂修饰的Bi_1.5Zn_1.0Nb_1.5O₇作为栅绝缘层的ZnO-TFTs结构,分析了SiO₂修饰对栅绝缘层和ZnO-TFTs性能的影响.结果表明,使用SiO₂修饰后,栅绝缘层和ZnO-TFTs的性能得到显著提高,使得ZnO-TFTs在下一代显示领域中具有非常广泛的应用前景.栅绝缘层的漏电流密度从4.5×10^-5A/cm²降低到7.7×10^-7A/cm²,粗糙度从4.52nm降低到3.74nm,ZnO-TFTs的亚阈值摆幅从10V/dec降低到2.81V/dec,界面态密度从8×10¹³cm^-2降低到9×10¹²cm^-2,迁移率从0.001cm²/（V·s）升高到0.159cm²/（V·s）.     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

Cl2-based dry etching of the AlGaInN system in inductively coupled plasmas

Cl₂-Based inductively coupled plasmas with low additional d.c. self-biases (−100 V) produce convenient etch rates (500–1500 Å·min⁻¹) for GaN, AlN, InN, InAlN and InGaN. A systematic study of the effects of additive gas (Ar, N₂, H₂), discharge composition and ICP source power and chuck power on etch rate and surface morphology has been performed. The general trends are to go through a maximum in etch rate with percent Cl₂ in the discharge for all three mixtures and to have an increase (decrease) in etch rate with source power (pressure). Since the etching is strongly ion-assisted, anisotropic pattern transfer is readily achieved. Maximum etch selectivities of approximately 6 for InN over the other nitrides were obtained.     

Fabrication and characterization of Si-MOSFET's with PECVDamorphous Ta2O5 gate insulator

Silicon MOS transistors having amorphous Ta₂O₅ insulator gates have been fabricated. The Ta₂O₅ films were deposited using a low pressure (a few mtorr) plasma-enhanced CVD process in a microwave (2.45 GHz) excited electron cyclotron resonance reactor. The source gas was TaF₅. Electrical characteristics of p-channel Al gate transistors are presented     

原子层沉积方法制备低温多层Al2O3/TiO2复合封装薄膜的研究

原子层沉积(ALD)方法可以制备出高质量薄膜,被认为是可应用于柔性有机电致发光器件(OLED)最有发展前景的薄膜封装技术之一。本文采用原子层沉积(ALD)技术,在低温(80℃)下,研究了Al₂O₃及TiO₂薄膜的生长规律,通过钙膜水汽透过率(WVTR)、薄膜接触角测试等手段,研究了不同堆叠结构的多层Al₂O₃/TiO₂复合封装薄膜的水汽阻隔特性,其中5 nm/5 nm×8 dyads(重复堆叠次数)的Al₂O₃/TiO₂叠层结构薄膜的WVTR达到2.1×10^-5 g/m²/day。采用优化后的Al₂O₃/TiO₂叠层结构薄膜对OLED器件进行封装,实验发现封装后的OLED器件在高温高湿条件下展现了较好的寿命特性。     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made     

One transistor ferroelectric memory with Pt/Pb5Ge3O11/Ir/poly-Si/SiO2/Si gate-stack

One transistor ferroelectric nonvolatile memory with gate stack of Pt/Pb₅Ge₃O₁₁/lr/poly-Si/SiO₂ /Si was successfully fabricated. This device features a saturated memory window of 3 V at a programming voltage of higher than 3 V from C-V and I-V measurements. The memory window decays rapidly within 10 seconds after programming, but remains stable at 1 V for up to 100 h. The "on" and "off" state currents are greater than 10 μA/μm and less 0.01 pA/μm, respectively, at a drain voltage of 0.1 V     

SiO2 masking against phosphorus diffusion using a P2O5 source

The masking of silicon against deep P₂O₅ diffusion by a 1-μ thick SiO₂ layer has been investigated. One aspect of masking failure has been related to mounds of phosphorus silicate glass, grown on the oxide during the P₂O₅ deposition, causing spot penetration of phosphorus through the oxide and into the silicon. Such spots can increase in density, diameter and depth during the subsequent diffusion. They link up and form a continuous, but not uniform n-type layer under the oxide. Residual water vapour in the deposition systems and particle deposits on wafers during washing have been shown to be the factors that contribute to the growth of mounds.     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents