A global model for rapid thermal processors

A simple model for the components that make up a rapid thermal processing system is given. These components are the furnace, the pyrometer used to measure temperature, and the control system that utilizes the pyrometer measurement to control the power to the lamps. The models for each of the components are integrated in a numerical code to give a computer simulation of the complete furnace operation. The simulation can be used to investigate the interaction of the furnace, temperature-sensing technique, and the control system. Therefore, the interplay of heat transfer (furnace) properties, optical (pyrometer) parameters, and control gains can be studied. The objective is to define variability in wafer temperature as process parameters change. The following three applications of the model are included: (1) a simulation of open-loop operation; (2) a simulation of the ramp up and subsequent operation with a step change in wafer optical properties; and (3) a simulation of the rapid thermal chemical vapor deposition of polysilicon on silicon oxide which demonstrates the applicability model for actual processes. A technique for correction of pyrometer output to improve temperature control is also presented     

Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

In situ measurement of wafer temperatures in a low pressurechemical vapor deposition furnace

Axial and radial temperature profiles within the wafer load of a multiwafer LPCVD furnace were measured in situ using a pair of instrumented wafers. The measurements confirm that the wafer load is not in thermal equilibrium with the furnace tube, as has been widely assumed in many modeling studies. The measurements confirm temperature variations predicted previously from a study of polysilicon film thickness profiles. Temperature variations were small for wafers near the center of the 150-wafer load. However, axial variations of up to 25°C and radial variations of up to 5°C were measured at the extremes of the wafer load. For a representative polysilicon deposition data set, axial and radial thin-film thickness variations were found to correlate closely with measured temperature variations. The temperature profile was found to be insensitive to gas composition and flowrate, establishing radiation as the dominant mode of heat transfer. A pair of polysilicon coated quartz radiation shields was shown to improve polysilicon film thickness uniformity both down the load (along the furnace axis) and across each wafer     

Prediction of defect onset conditions in heat cycling based on athermoelastic wafer model

A thermoelastic wafer model is proposed for predicting defect onset conditions during heat cycling in a furnace. This model is formulated for application to the plane stress state under thermal loading. The wafer temperature is calculated by a wafer temperature model proposed in a previous work. Predictions are tested by comparison with the thermal stresses resolved on the slip systems of the silicon crystal under the process conditions (i.e. furnace temperature, insertion velocity, and wafer spacing). When the proposed model is applied to 125-mm diameter and 150-mm-diameter wafers, it is shown that the thermal stress level is reduced to about a half by increasing the wafer spacing by a factor of two or three. Accordingly, the predicted defect onset results based on this model are in reasonable agreement with experiments     

Full Field Temperature Measurement of Specular Wafers During Rapid Thermal Processing

Many of the processes involved in the creation of semiconductor devices involve high-temperature processing of silicon wafers. The benefits of reduced thermal budget and faster cycle time make rapid thermal processing (RTP) a possible key technology for semiconductor manufacturing. However, the problem of nonuniform wafer temperature has prevented it from further spread among the industry. The first step in developing controls to maintain a uniform wafer temperature is accurate temperature measurement during processing. In this paper, a system was developed to exploit the specular reflectivity of silicon wafers and obtain a measurement of the wafer temperature profile. The spectral reflectivity is determined by measuring the intensity of an incident beam and the beam reflected from the wafer surface. With this measured reflectivity value the spectral-directional wafer emissivity was determined using Kirchhoff's law. The obtained emissivity then was used to calculate the wafer temperature profile from an image obtained with an infrared camera. An experimental study of the transmittance of an undoped silicon calibration wafer at an elevated temperature is also discussed     

Temperature measurement of metal-coated silicon wafers bydouble-pass infrared transmission

We report the measurement of the temperature of metal-coated silicon wafers by a double-pass infrared transmission technique. Infrared light incident on the backside of the wafer passes through the wafer, and is re-emitted out the backside after reflecting off the metal surface on the front side of the wafer. The temperature is inferred by the change in the re-emitted signal due to absorption in the wafer. The work has been demonstrated on double-polished wafers from 100°C to 550°C using wavelengths from 1.1 to 1.55 μm. A method for overcoming limitations of the present arrangement for wafers with a rough backside is proposed     

A technique for characterizing surface recombination in silicon wafers based on thermal-emission measurements

A noncontact technique for the measurement of the surface-recombination rate in silicon wafers is suggested. A wafer under study is excited optically in the spectral region of intrinsic absorption, and the excitation-wavelength dependence of the power of the wafer thermal emission beyond the intrinsic-absorption edge is examined. The surface-recombination rate is determined from the ratio of intensities of the wafer thermal emission in the wavelength range 3–5 μm recorded under excitation with two laser diodes with wavelengths of 863 and 966 nm. Wafers subjected to different surface treatments were tested; at 230°C, rates on the order of 10⁴ cm/s were measured after mechanical polishing and 10³ cm/s after etching in CP-4A etchant. The applicability of the method is discussed, and the measurement error as a function of the wafer and light-source parameters is considered.     

高温退火对铸造多晶硅片中位错密度的影响

对铸造多晶硅片进行了1 000~1 400℃的高温退火和不同方式冷却实验,用显微观察法对退火硅片及其相邻姊妹片位错密度进行了测量统计。研究了退火温度和冷却方式对铸造多晶硅片中位错密度的影响。结果证实:当退火温度在1 100℃及以下时,硅片的位错密度并没有降低反而增加了;当退火温度在1 320℃及以上时,硅片的位错密度明显降低,其幅度随温度提高增大;但退火后如断电随炉冷却而不控制冷却速率,位错密度又会提高。     

Aligned wafer bonding: A key to three dimensional microstructures

Successful fabrication of critically aligned three dimensional structures has been achieved by combining precision alignment procedures and techniques for direct silicon bonding. This produces three dimensional bonded layers that might include combinations of mechanical, electronic and/or optical elements formed in separate prefabricated layers. We call this techniquealigned wafer bonding. The precise aligned bonding of the features was done with an Optical AssociatesHyperline 400 Infrared Aligner. This machine can hold two imprinted wafers face to face while projecting an infrared image of the surfaces to a viewing screen. An array of alignment marks were etched into the surface of silicon wafers with hot potassium hydroxide. These V-grooves were then precisely aligned and the wafers were brought into contact for initial bonding. Subsequent high temperature annealing was used to strengthen and complete the chemical bonding. The instrumentation used in this work required alignment features with a vertical dimension of 30 micrometers to produce a suitable infrared image. We found that the apparent size of the images produced by the optical system limited the accuracy in precision alignment. However, with reduced wafer separation, we achieved wafer alignment with an accuracy of better than 5 micrometers. This technique would generally be used for the precision alignment and bonding of complementary micromechanical, electrical, or optical structures during the formation of three dimensional devices. The details of the aligned wafer bonding and its applications are presented.     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

Easy-to-use surface passivation technique for bulk carrier lifetime measurements on silicon wafers

A novel, easily applicable surface passivation technique is presented, which, in combination with contactless photocoductance decay (PCD) measurements, allows a quick estimation of the bulk carrier lifetime of crystalline silicon wafers. The proposed passivation technique requires neither a chemical pre-cleaning of the silicon wafer nor expensive instrumentation. On both surfaces of the wafer a thin varnish film is deposited using a spinner. Subsequently, both surfaces of the coated silicon wafer are charged by means of a corona chamber. Using microwave-detected PCD measurements, we experimentally demonstrate that this novel surface passivation scheme provides differential surface recombination velocities in the 30–70 cm s⁻¹ range on p-as well as n-type silicon wafers. © 1998 John Wiley & Sons, Ltd.     

Detection of oxygen concentration in silicon wafers using a tunable diode laser

Control of the oxygen concentration in silicon wafers is important for the fabrication of high quality integrated circuits. Techniques for the fast detection of oxygen would be desirable for production line quality control. The oxygen concentration in silicon has traditionally been measured by a Fourier transform infrared spectrometer (FTIS). Due to the slow response time (1-10 min), it is not suitable for wafer screening. In this report, we describe a diode laser spectroscopy technique for the fast (10 ms) detection of oxygen in production line silicon wafers. The results are in good agreement with those measured by the Fourier transform technique.     

Effect of nanotopography in direct wafer bonding: modeling and measurements

Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

真空键合技术制作三层结构的MEMS器件的研究

采用真空键合技术 ,成功地将表面具有深度不同的硅槽或框架结构的硅圆片与另外两个硅圆片贴合形成三层夹心结构 ,经高温退火处理 ,得到一种粘合牢固的硅“三明治”体。这种“三明治”体的上下两个硅片仍可进行IC加工 ,为MEMS传感部分和测试电路的三维一体化集成打下了坚实的基础     

Features of defect formation under the thermal treatment of dislocation-free single-crystal large-diameter silicon wafers with the specified distribution of oxygen-containing gettering centers in the bulk

Possibilities of obtaining a defect-free layer in wafers of dislocation-free single-crystal silicon subjected to rapid thermal annealing (RTA) are analyzed. The application of RTA is based on the possibility of effectively affecting the distribution profile of the density of oxygen precipitates over the wafer thickness by means of controlling the distribution profiles of the vacancies and interstitial atoms. However, the solution of this important task encounters the problem of the appearance of large local stresses in the vicinity of the fastening supports of a large-diameter silicon wafer and its bending in the course of RTA, which are caused by its own weight. Using mathematical modeling of the three-dimensional stress-strain state and defect formation in large-diameter silicon wafers in the course of RTA, various methods of fastening the wafers are considered and the possibilities of lowering the stress-strain state of the silicon wafer are determined. A mathematical model taking into account the diffusion-recombination processes of vacancies and interstitial silicon atoms, as well as the formation of vacancy clusters is proposed to describe the defect formation in the course of RTA. Based on this model, temperature-temporal parameters of RTA, which correspond to the required (depleted near the surface) concentration profile of the vacancies and the density and size of the vacancy clusters over the wafer thickness, are determined (heating time, holding time at the highest temperature, the cooling rate of the wafer). The results of the calculations are verified for test samples using optical microscopy and transmission electron microscopy (OM and TEM).     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

The Effect of Thermal Shocks on the Stresses in a Sapphire Wafer

Sapphire wafers can experience temperature variations during processing in a furnace, which in turn can cause large deformation and stresses in the wafers. This paper aims to reveal the mechanism of stress development and evolution in sapphire wafers during thermal shocks, as well as the dependence of the stresses on some process parameters. Finite-element stress analysis was conducted on a single sapphire wafer subjected to thermal shocks. The results show that the thermal gradient in the radial direction induces high stresses even in mechanically unrestrained wafers. The largest stress components occur at the wafer edge as the largest normal stresses are circumferential; whereas the maximum tensile stress is realized upon cooling, the highest value of the maximum shear stress and the minimum compressive stress eventuate in the heating-up phase. The normal stresses have a parabolic distribution in the radial direction. It was found that holding the furnace temperature leads to a more uniform temperature distribution across the wafer but brings about higher tensile stresses in the cooling phase