Broadband transport — the synchronous digital hierarchy

All data networks require a physical transmission medium to convey information between network nodes. Within a local environment this physical medium might, for example, take the form of an Ethernet LAN, but wide area connections are provided using telecommunications constant bit rate transmission equipment. Furthermore, the assumption that data networking is simply the provision of WAN connectivity for large corporate networks is becoming dated. The explosion of interest in the Internet means that, for transport networks, the term data may encompass voice, video and multimedia applications for delivery to both home and office. This places additional requirements on the network infrastructure as each service has specific transport requirements.Network operators are currently in the process of deploying core networks of equipment conforming to the ITU-T Recommendations for a synchronous digital hierarchy (SDH), but many networks also contain a significant proportion of older transmission technologies. This paper provides a review of transmission technology and describes the impact of such networks on the transport of data.     

A synchronous digital hierarchy network management system

The critical issues in multivendor environments and operation systems of telecommunication networks essential to speeding up the handling of service orders and service restoration after failures are discussed. To overcome these problems as the software backlog grows, the authors propose the application of a telecommunications management network (TMN) architecture together with an object-oriented network resource (ONR) model. The second phase of the synchronous digital hierarchy (SDH) network management system, which is based on the TMN architecture and ONR model, is examined     

Clock distribution networks in synchronous digital integratedcircuits

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed     

Ku-band satellite digital transmission systems

A nation-wide data communications service is being placed in service by a major telecommunications carrier. This service will rely on a satellite network being provided and installed by Harris Satellite Communications Corporation. The network supports information data rates from 56 kb/s to 2·048 Mb/s. This data communications network has been architectured to include a number of innovative monitor and control functions, up-link power control, modular equipment shelter design and a modular antenna/feed subsystem. This paper will detail this application.     

The impact of synchronous digital hierarchy on digital microwaveradio: a view from Australasia

The recently agreed upon synchronous digital hierarchy (SDH) standard, which will provide a means to manage, multiplex, and access various forms of digital traffic in an economical and efficient manner, is described, and it is explained how radio systems can be deployed in SDH networks. This is followed by a discussion on the technical requirements for SDH digital radio relay system equipment. Frequency planning issues are considered. Gross transmission capacities that can be realized for various options of modulation schemes and RF channel spacing are discussed     

The synchronous digital hierarchy. II. Survival of the fittest

For pt.I see ibid., vol.37, no.5, p.185-9, 1991. The authors explain how the synchronous digital hierarchy (SDH) offers a solution the problems caused by the digitalisation of the world's telecommunications networks. The principles and the pros and cons of SDH are also outlined     

Time signal distribution in communication networks based onsynchronous digital hierarchy

A new method that uses round-trip paths to accurately measure transmission delay for submicrosecond time synchronization in synchronous digital hierarchy (SDH) networks is proposed. Since the proposed system uses virtual container-3 (VC-3) signal as the time reference signals, existing SDH equipment can be used without any changes. The feature of this method is that it separately measures the initial round-trip path delay and subsequent variations in round-trip path delay. The initial uncertain delay due to the administrative unit-3 (AU-3) pointer operations in SDH equipment is determined by controlling the reference clock of the equipment. The characteristics of the equipment delay caused by the pointer operations are also described. In an experiment with actual SDH equipment, the error in initial delay determination was suppressed to 30 ns. The delay variation measurement of the round-trip path is not affected by the pointer operation in the proposed method. The precision of delay variation measurement can be better than 10 ns     

Clock frequency and latency in synchronous digital systems

The tradeoffs in the design of synchronous digital systems between clock frequency and latency in terms of the circuit characteristics of a pipelined data path are described. A design paradigm relating latency and clock frequency as a function of the level of pipelining is developed for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems which describe these performance parameters in terms of the delays of the logic, interconnect, registers, clock skew, and the number of logic states. These results provide an approach to the design of those synchronous digital systems in which latency and clock frequency are of primary importance. From the behavioral specifications for the proposed system, the designer can use these results to select the best logic architecture and the best available device technology to determine if the performance specifications can be satisfied, and, if so, what design options are available for optimization of other system attributes, such as area     

Pipelining of high performance synchronous digital systems

A new approach is described to the design of those synchronous digital systems in which the performance parameters latency and clock frequency are of primary importance. Specifically, the trade-off between clock frequency and latency is analysed in terms of the circuit characteristics of a pipelined data path. A design paradigm relating latency and clock frequency as a function of the level of pipelining is described for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems from which the optimal level of pipelining can be determined in terms of the delays of logic, interconnect, and registers, and the clock skew and number of logic stages.     

The synchronous digital hierarchy. I. The origin of the species

Throughout the world, public network operators are set to begin trials of what are known as synchronous transmission systems. The authors look at plesiochronous digital hierarchy, its successor, and describe the nature of the new transmission systems, indicate why they are needed, and identify some of the benefits they will bring to operators and users alike     

Analysis of satellite broadcasting systems for digital television

The concept of digital direct satellite broadcasting (D-DBS), which allows unprecedented flexibility by providing a large number of audio-visual services, is introduced. The concept assumes an information rate of about 40 Mb/s, which is compatible with practically all present-day transponders. After discussion of the general system concept, the optimization procedure is introduced, and results of the transmission system optimization are presented. Channel distortion and uplink/downlink interference effects are taken into account by means of a time domain system computer simulation approach. It is shown, by means of link budget analysis, how a medium-power direct-to-home TV satellite can provide multimedia services to users equipped with small (60-cm) dish antennas     

Multilevel trellis-coded modulations for mobile multimedia satellite systems using synchronous CDMA

In this paper the performance of multilevel trellis-coded modulations (MTCMs) for satellite mobile multimedia systems using synchronous CDMA is investigated. A model for the multiple-access interference arising from the non-orthogonality of the spreading waveforms is developed for different modulation and spreading schemes and transmission over the mobile satellite channel. Using this model, the performance of MTCMs for synchronous CDMA is analysed and compared with the Ungerboeck and Schegel–Costello trellis-coded modulation (TCM) designs. The impact on the transmission of synchronization errors between the different users is presented and the power control requirements are derived. © 1998 John Wiley & Sons, Ltd.     

Innovations in microwave filters and multiplexing networks forcommunications satellite systems

The evolution of microwave filters and multiplexers for space application is described. The many advances are described within the context of the design of the overall communication subsystem. Emphasis is placed on the multipaction and passive intermodulation (PIM) considerations in designing high-power multiplexers. The impact of microwave filter technology in the channel characterization of satellite systems is described. The future directions of research and development are briefly discussed     

Precision time-transfer in transport networks using digitalcross-connect systems

A technique for precise synchronization of the time-of-day clocks in networks of digital cross-connect systems (DCSs) is described. This method is intended to enhance the performance of reconfigurable transport networks and is specifically devised to exploit the fine time resolution of the carrier signals to which a DCS has direct access. The resulting scheme is a master-slave, multisite, implicitly delay compensated, nonhierarchical time-transfer method with a theoretical precision of one bit time at the carrier rate. In practice, precision is limited by transmission span delay asymmetries but residual time errors of under 1 μs are predicted. The method is intended for n/ n space-switching DCS, but other DCS properties can be accommodated. Requirements for DCS equipment design are given, including a generic circuit module for DCS hardware support of the time transfer function. The proposed method applies to DS-3 networks or synchronous optical networks and requires no change in the standards. Measurement or improved estimation of characteristic span delay asymmetries is recommended to refine the preliminary performance estimate     

TCP-Peachtree: a multicast transport protocol for satellite IP networks

In this paper, a reliable multicast transport protocol TCP-Peachtree is proposed for satellite Internet protocol (IP) networks. In addition to the acknowledgment implosion and scalability problems in terrestrial wirelined networks, satellite multicasting has additional problems, i.e., different multicast topology, different type of congestion control problems, and low bandwidth feedback link. In TCP-Peachtree, the modified B+ tree logical hierarchical structure is used to form dynamic multicast groups. Local error recovery and acknowledgment (ACK) aggregations are performed within each subgroup and also via logical subgroups. In order to avoid the overall performance degradation caused by some worst receivers, a local relay scheme is designed. Two new algorithms, jump start and quick recovery, which are based on the usage of a type of low-priority segments called NIL segments, are proposed for congestion control. NIL segments are used to probe the availability of network resources and also for error recovery. The delayed selective acknowledgment (SACK) scheme is adopted to address the bandwidth asymmetry problems and a hold state is developed to address persistent fades. The simulation results show that the congestion control algorithms of TCP-Peachtree outperform the TCP-NewReno when combined with our hierarchical groups and improve the throughput performance during rain fades. It is also shown that TCP-Peachtree achieves fairness and is very highly scalability.     

Innovative hybrid optical/digital ultra-fast packet-switched processor for meshed satellite networks

This paper describes the architectural study of an innovative ultra-fast packet-switched transparent processor dealing efficiently with unicast and multicast applications. The proposed architecture aims at outperforming current packet processor architectures in terms of total throughput and efficiency. In order to cope with the limitations of today's on board processors, three new concepts are introduced: transparent burst switching, channel multiplexing, and bandwidth asymmetry . Some of these concepts are already well known in the field of optical terrestrial networks but need further improvements and adaptations to cope with the requirements of satellite processors and systems. Transparent burst switching is used to enhance the transparency of the processor: the packet payload is processed transparently and only the header is demodulated onboard. The channel multiplexing and bandwidth asymmetry techniques are used to consolidate bufferless switch architectures, which appear to be very attractive for increasing the overall throughput of switches. Finally, the paper introduces an innovative efficient and scalable hybrid optical/digital implementation of this processor. The focus here is on a satellite-switched code/time-division multiple-access type of system but the results and concepts provided in this paper can apply to other satellite-switched systems.     

IPv6 networks over DVB‐RCS satellite systems

Satellite plays an important role in global information infrastructure (GII) and next generation networks (NGNs). Similarly, satellite communication systems have great advantages to support IPv6 (Internet Protocol version 6) networks as a technology that allows universal access to broadband e‐services (audio, video, VPN, etc.). In the context of DVB‐S2 (digital video broadcast‐satellite) and DVB‐RCS (digital video broadcast‐return channel via satellite) standards, this paper presents the current SatSix project (satellite‐based communications systems within IPv6 networks) within the European 6th Framework Programme, which is implementing innovative concepts and effective solutions (in relation with the economical cost) for broadband satellite systems and services using the technology presented above. This project is promoting the introduction of the IPv6 protocol into satellite‐based communication systems. Moreover, through SatSix, the industry is addressing the next generation Internet, IPv6. It also enhances its competitive position in satellite broadband multimedia systems by exploiting the common components defined by the European DVB‐S2 and DVB‐RCS satellite broadband standards. Copyright © 2007 John Wiley & Sons, Ltd.     

A synchronous digital hierachy based dynamic error correction technique for wavelength division multiplexing networks

This paper proposes a new synchronous digital hierarchy (SDH) based forward error correction (FEC) scheme for wavelength division multiplexing (WDM) networks. In this scheme, a dedicated WDM channel is used to transport the FEC redundant bits. This paper also proposes the use of error location analysis of the FEC correctable bits to identify the pattern of errors, combined with the seriousness of errors obtained from B2-byte analysis to decide as to the suitable FEC code to be assigned to the payload channels. The proposed FEC scheme is studied not only under the typical Poisson errors but also the bursty errors. Simulation results show that the proposed FEC scheme performs significantly better than the existing FEC schemes. It is also shown that the performance of the proposed FEC scheme on bursty errors is independent of the line rates, whereas the existing FEC schemes either cannot support bursty errors or degrades with line rates.     

Accurate and efficient simulation of synchronous digital switching noise in systems on a chip

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.