恒压应力下超薄Si3N4/SiO2叠层栅介质与SiO2栅介质寿命比较

以等效氧化层厚度(EOT)同为2.1nm的纯SiO2栅介质和Si3N4/SiO2叠层栅介质为例,给出了恒定电压应力下超薄栅介质寿命预测的一般方法,并在此基础上比较了纯SiO2栅介质和Si3N4/SiO2叠层栅介质在恒压应力下的寿命.结果表明,Si3N4/SiO2叠层栅介质比同样EOT的纯SiO2栅介质有更长的寿命,这说明Si3N4/SiO2叠层栅介质有更高的可靠性.     

超薄Si3N4/SiO2(N/O) stack栅介质及器件

成功制备了EOT(equivalent oxide thickness)为2.1nm的Si3N4/SiO2(N/O) stack栅介质,并对其性质进行了研究.结果表明,同样EOT的Si3N4/SiO2 stack栅介质和纯SiO2栅介质比较,前者在栅隧穿漏电流、抗SILC性能、栅介质寿命等方面都远优于后者.在此基础上,采用Si3N4/SiO2 stack栅介质制备出性能优良的栅长为0.12μm的CMOS器件,器件很好地抑制了短沟道效应.在Vds=Vgs=±1.5V下,nMOSFET和pMOSFET对应的饱和电流Ion分别为584.3μA/μm和-281.3μA/μm,对应Ioff分别是8.3nA/μm和-1.3nA/μm.     

超薄Si3N4/SiO2（N/O）stack栅介质及器件

成功制备了EOT(equivalent oxide thickness)为2.1nm的Si3N4/SiO2(N/O) stack栅介质,并对其性质进行了研究．结果表明，同样EOT的Si3N4/SiO2 stack栅介质和纯SiO2栅介质比较，前者在栅隧穿漏电流、抗SILC性能、栅介质寿命等方面都远优于后者．在此基础上,采用Si3N4/SiO2 stack栅介质制备出性能优良的栅长为0.12μｍ的CMOS器件，器件很好地抑制了短沟道效应．在Vds=Vgs=±1.5V下，nMOSFET和pMOSFET对应的饱和电流Ion分别为584.3μA/μｍ和－281.3μA/μｍ，对应Ioff分别是8.3nA/μｍ和－1.3nA/μｍ．     

离子注入氮化薄SiO_2栅介质的特性

研究了通过多晶硅栅注入氮离子氮化 10 nm薄栅 Si O2 的特性 .实验证明氮化后的薄 Si O2 栅具有明显的抗硼穿透能力 ,它在 FN应力下的氧化物陷阱电荷产生速率和正向 FN应力下的慢态产生速率比常规栅介质均有显著下降 ,氮化栅介质的击穿电荷 (Qbd)比常规栅介质提高了 2 0 % .栅介质性能改善的可能原因是由于离子注入工艺在栅 Si O2 中引进的 N+离子形成了更稳定的键所致     

3—6nm超薄SiO_2栅介质的特性

采用栅氧化前硅表面在 H2 SO4/ H2 O2 中形成化学氧化层方法和氮气稀释氧化制备出 3.2、 4和 6 nm的 Si O2超薄栅介质 ,并研究了其特性 .实验结果表明 ,恒流应力下 3.2和 4nm栅介质发生软击穿现象 .随着栅介质减薄 ,永久击穿电场强度增加 ,但恒流应力下软击穿电荷下降 .软击穿后栅介质低场漏电流无规则增大 .研究还表明 ,用软击穿电荷分布计算超薄栅介质有效缺陷密度比用永久击穿场强分布计算的要大 .在探讨软击穿和永久击穿机理的基础上解释了实验结果     

硅衬底注氮方法制备超薄SiO2栅介质

利用栅氧化前在硅衬底内注氮可抑制氧化速率的方法,制得3.4nm厚的SiO2栅介质,并将其应用于MOS电容样品的制备.研究了N+注入后在Si/SiO2中的分布及热退火对该分布的影响;考察了不同注氮剂量对栅氧化速率的影响.对MOS电容样品的I-V特性,恒流应力下的Qbd,SILC及C-V特性进行了测试,分析了不同氧化工艺条件下栅介质的性能.实验结果表明:注氮后的热退火过程会使氮在Si/SiO2界面堆积;硅衬底内注入的氮的剂量越大,对氧化速率的抑制作用越明显;高温栅氧化前进行低温预氧化的注氮样品较不进行该工艺步骤的注氮样品具有更低的低场漏电流和更小的SILC电流密度,但二者恒流应力下的Qbd值及高频C-V特性相近.     

超薄Si3N4/SiO2叠层栅介质可靠性研究

实验成功地制备出等效氧化层厚度为亚2nm的Nitride/Oxynitride(N/O)叠层栅介质难熔金属栅电极PMOS电容并对其进行了可靠性研究.实验结果表明相对于纯氧栅介质而言,N/O叠层栅介质具有更好的抗击穿特性,应力诱生漏电特性以及TDDB特性.进一步研究发现具有更薄EOT的难熔金属栅电极PMOS电容在TDDB特性以及寿命等方面均优于多晶硅栅电极的相应结构.     

离子注入氮化薄SiO2栅介质的特性

研究了通过多晶硅栅注入氮离子氮化10nm薄栅SiO2的特性.实验证明氮化后的薄SiO2栅具有明显的抗硼穿透能力,它在FN应力下的氧化物陷阱电荷产生速率和正向FN应力下的慢态产生速率比常规栅介质均有显著下降,氮化栅介质的击穿电荷(Qbd)比常规栅介质提高了20%.栅介质性能改善的可能原因是由于离子注入工艺在栅SiO2中引进的N+离子形成了更稳定的键所致.     

氮注入多晶硅栅对超薄SiO_2栅介质性能的影响

p+ 多晶硅栅中的硼在 Si O2 栅介质中的扩散会引起栅介质可靠性退化 ,在多晶硅栅内注入 N+ 的工艺可抑制硼扩散 .制备出栅介质厚度为 4 .6 nm的 p+栅 MOS电容 ,通过 SIMS测试分析和 I- V、C- V特性及电应力下击穿特性的测试 ,观察了多晶硅栅中注 N+工艺对栅介质性能的影响 .实验结果表明 :在多晶硅栅中注入氮可以有效抑制硼扩散 ,降低了低场漏电和平带电压的漂移 ,改善了栅介质的击穿性能 ,但同时使多晶硅耗尽效应增强、方块电阻增大 ,需要折衷优化设计 .     

3-6nm超薄SiO2栅介质的特性

采用栅氧化前硅表面在H2SO4/H2O2中形成化学氧化层方法和氮气稀释氧化制备出3.2、4和6nm的SiO2超薄栅介质,并研究了其特性.实验结果表明,恒流应力下3.2和4nm栅介质发生软击穿现象.随着栅介质减薄,永久击穿电场强度增加,但恒流应力下软击穿电荷下降.软击穿后栅介质低场漏电流无规则增大.研究还表明,用软击穿电荷分布计算超薄栅介质有效缺陷密度比用永久击穿场强分布计算的要大.在探讨软击穿和永久击穿机理的基础上解释了实验结果.     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²     

Tunneling leakage current in ultrathin (<4 nm) nitride/oxidestack dielectrics

The leakage current in high-quality ultrathin silicon nitride/oxide (N/O) stack dielectric is calculated based on a model of one-step electron tunneling through both the nitride and the oxide layers. The results show that the tunneling leakage current in the N/O stack is substantially lower than that in the oxide layer of the same equivalent oxide thickness (EOT). The theoretical leakage current in N/O stack has been found to be a strong function of the nitride/oxide EOT ratio: in the direct tunneling regime, the leakage current decreases monotonically as the M/O ratio increases, while in the Fowler-Nordheim regime the lowest leakage current is realized with a N/O EOT ratio of 1:1. Due to the asymmetry of the N/O barrier shape, the leakage current under substrate injection is higher than that under gate injection, although such a difference becomes smaller in the lower voltage regime. Experimental data obtained from high quality ultrathin N/O stack dielectrics agree well with calculated results     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

The material and electrical properties of HfO2 high-k gate dielectric are reported.In the first part,the band alignment of HfO2 and (HfO2)x(Al2O3)1-x to (100)Si substrate and their thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO2)x(Al2O3)1-x,the valence band offset,and the conduction band offset between (HfO2)x(Al2O3)1-x and the Si substrate as functions of x are obtained based on the XPS results.Our XPS results also demonstrate that both the thermal stability and the resistance to oxygen diffusion of HfO2 are improved by adding Al to form Hf aluminates.In the second part,a thermally stable and high quality HfN/HfO2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage,and work function (close to Si mid-gap) of HfN/HfO2 gate stack are demonstrated even after 1000℃ post-metal annealing(PMA),which is attributed to the superior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/HfO2 interface.Therefore,even without surface nitridation prior to HfO2 deposition,the EOT of HfN/HfO2 gate stack has been successfully scaled down to less than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.The last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO2 gate dielectric.The excellent thermal stability of the HfN/HfO2 gate stack enables its use in high temperature CMOS processes.The replacement of HfN with other metal gate materials with work functions adequate for n- and p-MOS is facilitated by a high etch selectivity of HfN with respect to HfO2,without any degradation to the EOT,gate leakage,or TDDB characteristics of HfO2.     

Hole tunneling current through oxynitride/oxide stack and the stackoptimization for p-MOSFETs

A systematic study on hole-tunneling current through both oxynitride and oxynitride/oxide (N/O) stack is for the first time presented based on a physical model. The calculations are in good agreement with the available experimental data. With a given equivalent oxide thickness (EOT), and under typical operating gate voltages (|Vg|<2 V), hole-tunneling current (essentially the gate current) is found to be lowest through the oxynitride or N/O stack with ~33% of nitrogen (N). An optimized N/O stack structure with 33% (atomic percentage) nitrogen and with a 3 Å oxide layer for keeping acceptable channel interface quality is proposed to project the N/O gate dielectrics scaling limit using in MOSFETs     

Atomic Layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics for future high-speed DRAM with enhanced reliability

Atomic layer-deposited (ALD) Si-nitride/SiO/sub 2/ stack gate dielectrics were applied to high-performance transistors for future scaled DRAMs. The stack gate dielectrics of the peripheral pMOS transistors excellently suppress boron penetration. ALD stack gate dielectrics exhibit only slightly worse negative-bias temperature instability (NBTI) characteristics than pure gate oxide. Enhanced reliability in NBTI was achieved compared with that of plasma-nitrided gate SiO/sub 2/. Memory-cell (MC) nMOS transistors with ALD stack gate dielectrics show slightly smaller junction leakage than those with plasma-nitrided gate SiO/sub 2/ in a high-drain-voltage region, and have identical junction leakage characteristics to transistors with pure gate oxide. MCs having transistors with ALD stack gate dielectrics and those with pure gate oxide have the identical retention-time distribution. Taking the identical hole mobility for the transistors with ALD stack gate dielectrics to that for the transistors with pure gate oxide both before and after hot carrier injection (previously reported) into account, the ALD stack dielectrics are a promising candidate for the gate dielectrics of future high-speed, reliable DRAMs.     

Performance and reliability of low-temperature polysilicon TFT with a novel stack gate dielectric and stack optimization using PECVD nitrous oxide plasma

This paper proposes a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si thin-film transistors, composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O plasma. The novel stack gate dielectric exhibits a very high electrical breakdown field of 8.5 MV/cm, which is approximately 3 MV/cm higher than traditional PECVD TEOS oxide. The novel stack oxide also has better interface quality, lower bulk-trap density, and higher long-term reliability than PECVD TEOS dielectrics. These improvements are attributed to the formation of strong Si/spl equiv/N bonds of high quality ultra-thin oxynitride grown by PECVD N/sub 2/O plasma, and the reduction in the trap density at the oxynitride/poly-Si interface.     

堆叠栅介质MOS器件栅极漏电流的计算模型

采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。     

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride（N/O）stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated，and ultra thin (＜2 nm＝ N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.     

超薄氮氧叠层栅介质的金属栅pMOS电容的电学特性

研究了高质量超薄氮化硅/氮氧化硅(N/O)叠层栅介质的金属栅pMOS电容的电学特性,制备了栅介质等效厚度小于2nm的N/O复合叠层栅介质,该栅介质具有很强的抗硼穿通能力和低的漏电流.实验表明这种N/O复合栅介质与优化溅射W/TiN金属栅相结合的技术具有良好的发展前景.