A 90 nm CMOS 15/60 GHz frequency quadrupler

The design and characterisation of a 60?GHz frequency quadrupler implemented in a conventional 90?nm CMOS technology is presented. The proposed fully differential frequency quadrupler is formed by properly combining a 15?GHz to 30?GHz doubler, two 30?GHz amplifiers, a polyphase filter, a 30 to 60?GHz doubler and two 60?GHz amplifiers. The proposed design is based on a differential architecture and achieves enhanced characteristics in terms of harmonics rejection, bandwidth, power consumption and die area. Conversion loss of 9.3?dBm at 60?GHz with 1.1?dBm input power is achieved. The 3?dB bandwidth lies between 51.5?GHz and 61?GHz, while the total current consumption is 100?mA from a 1.2?V supply voltage for the fully balanced implementation.     

90nm CMOS工艺低功耗20GHz比较器设计

A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic （SCL） topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm^2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second （GSps） with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.     

基于90 nm CMOS工艺的37 GHz分频器

对高速分频器的注入锁定特性进行了研究,并实现了一个基于电流模逻辑的分频器。该分频器采用了电感峰值技术,分频范围可达25~37.3 GHz,电源电压为1.2 V,功耗为24 mW。芯片采用TSMC 90 nm CMOS工艺设计制造,并给出了测试结果。     

基于90nm CMOS工艺的12GHz二分频器

采用90 nm CMOS工艺,实现了一个基于电流模式逻辑的12 GHz二分频器.该分频器具有很宽的锁定频率范围(1～12 GHz),在输入信号频率为8 GHz时,输入灵敏度达到-30 dBm.分频器工作在1.2 V电源电压下,消耗的电流大约为1.5 mA.给出了该设计的后仿真结果.     

A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 × 700 μm². Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of −110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.     

基于90nm CMOS工艺2.8GHz电荷泵锁相环的设计

为实现超宽带无线收发片上系统中低相位噪声、相互正交的两路本振信号,并避免高集成度环境下发射机中大功率载波信号对锁相环的牵引,本文采用SMIC 90 nm工艺设计了一款振荡频率二倍载波频率的电荷泵整数分频锁相环.实现过程中,本文提出了分别在鉴频鉴相器上开关控链路和下开关控制链路上插入传输门的方法,减小死区的同时降低电流失配对环路的影响;采用了低分频系数和高频率的参考信号方案改善了环路的相位噪声;采用了电容阵列的方式来校正压控振荡器方案以减小工艺偏差以及寄生参数对调谐范围的影响.本文完成锁相环版图设计后,提取了各模块的参数并进行了后仿真.SPECTRE仿真结果表明:该锁相环的相位噪声为-125 dBc/Hz@1MHz,且通过差分二分频可获得两路相互正交的本振信号.     

94 GHz down-conversion mixer with gain enhanced Gilbert cell in 90 nm CMOS

This paper introduces an adaptive semiblind background calibration of timing mismatches in a two-channel time-interleaved analog-to-digital converter (TIADC). By injecting a test tone at the frequency of half the overall sampling frequency of TIADC, the timing mismatch between two sub-ADCs can be quickly estimated with great accuracy without affecting the normal operation of the TIADC. The estimated coefficient can then be used in compensation module formed by a fixed structure to calibrate the timing mismatches. Simulation results demonstrate the effectiveness of the proposed estimation and correction technique.     

基于90nm CMOS工艺的60GHz射频接收前端电路设计

设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59～64 GHz的微波信号下变频至5～10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5～17.5 dB,双边带噪声因子为6.4～7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。     

A hybrid CT/DT double-sampled SMASH Σ? modulator for broadband applications in 90?nm CMOS technology

In this paper, a hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise shaping (MASH) sigma?Cdelta (????) modulator architecture for broadband applications is presented. The double-sampling technique is employed in the DT second-stage modulator in order to reduce the power consumption of the overall modulator. Flat and unity signal transfer functions are used in the first- and second-stage modulators, respectively, to relax the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first-stage CT modulator. The proposed structure is insensitive to the amplifier limited dc gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. As a design example, the proposed MASH 2-2 modulator is designed in a 90?nm CMOS technology with 1?V power supply. Circuit level simulation results with HSPICE achieve the maximum SNDR of 74.8?dB and dynamic range of 76.5?dB in 12.5?MHz bandwidth with 17?mW power consumption while operating at 200?MHz sampling rate.     

A noise-shaping SAR ADC for energy limited applications in 90 nm CMOS technology

In this paper, an ultra-low-power successive approximation register analog-to-digital converter (ADC) for energy limited applications is presented. The ADC resolution is enhanced by using a noise-shaping technique which does not need any integrator and only uses a finite impulse response (FIR) filter. To provide a first-order noise-shaping, the quantization error is firstly extracted by using the digital-to-analog converter (DAC) dummy capacitor and it is then employed in the error feedback scheme. The proposed structure employs a low-gain and low-swing operational transconductance amplifier (OTA) to realize the FIR filter which operates only at the sampling phase. To minimize the power consumption of the ADC analog part, the OTA is powered off during the conversion phase. The proposed ADC is designed and simulated in a 90 nm CMOS technology using Spectre with a 0.5 V single power supply. The simulated ADC uses a fully-differential 8-bit charge redistribution DAC with an oversampling ratio of 8 and achieves 10.7-bit accuracy. The simulated average power consumption is 4.53 μW and the achieved maximum SNDR and SFDR are 66.1 and 73.1 dB, respectively, resulting in a figure of merit of 27.6 fJ/conversion-step.     

A highly linear CMOS transconductance amplifier in 180?nm process technology

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180?nm CMOS process technology with 1.8?V power supply. Simulation results show third order harmonic distortion (HD ₃) of ?70?dB for 600?mV_pp input signal. For 1% transconductance variation the linear range is about 1.2?V_pp. The input referred noise of the transconductor is $70\,\hbox{nV}/\sqrt{\text {Hz}}$ at 10?MHz. The quiescent power consumption is only 450???W.     

A 5 GHz 90-nm CMOS all digital phase-locked loop

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of −125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm² and the current consumption is 30 mA from a 1.2 V supply.     

Design of an ultra small passive balun in CMOS 65?nm technology for 60?GHz applications

In this paper a new procedure for the spiral Marchand balun design is shown and demonstrated. The size reduction for this component is fundamental to obtain a high level of integration for the radio frequency analog circuits. This work shows a micro-structure that, working as a balun, achieves good performance in phase and amplitude balance, while maintaining minimum size. These results were achieved by performing an accurate theoretical analysis followed by an electromagnetic simulation of the structure. A set of equations are proposed to describe the component behavior and the measurements show a strong agreement with the simulations confirming the quality of the design flow. The balun shows a maximum of 1.5 dB of insertion loss, with 0.1 dB of amplitude imbalance. The phase imbalance reach as a maximum of 7° at 65?GHz. The total occupied area of the balun remain below to 0.01?mm².     

飞利浦开始大批量生产90nm CMOS产品

皇家飞利浦电子公司日前宣布有三款关键的90nm CMOS产品正式在法国Crolles的Crolles2联盟晶圆生产厂投入大批量生产，其中一款产品每月的发货量已经超过100万片。飞利浦公司的这三款产品是用于高度集成的系统级封装（System—in—Package，SiP）连接解决方案的基带芯片。通过这三款产品，飞利浦展示了90nm CMOS工艺在缩小此类解决方案在尺寸、降低功耗以及使其保持价格竞争力方面的优势。     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

采用90nm CMOS工艺的低功耗VCO

比利时的大学校际微电子中心(IMEC)的研究人员以及瑞典的同行采用90nm硅CMOS工艺开发出低功率压控振荡器(VCO)。这些低功耗压控振荡器达到高性能的关键是采用了基于圆片级封装技术的高Q值电感器。他们制作出两个5GHzVCO和一个15GHzVCO。两个5GHzVCO的功耗仅0.33mW,1MHz频偏下的     

90nm CMOS用多晶SiGe栅极技术

在最先进的器件里,为了提高晶体管性能,在工艺上几乎是年年都在消减栅极绝缘层厚度。另一方面,作为晶体管的栅极,在过去的30多年里都是一直在使用多晶硅材料,但是随着栅极绝缘层薄膜化,由多晶硅栅极电极内的载流子耗尽化所造成的性能低下问题也日益严重起来。为了简单表示栅极电极的载流子耗尽化的情况,请参阅图1所示模     

一种65 nm CMOS 60 GHz高增益功率放大器

设计了一种基于65 nm CMOS工艺的60 GHz功率放大器。采用共源共栅结构与电容中和共源级结构相结合的方式来提高功率放大器的增益,并采用两路差分结构来提高输出功率。采用片上变压器作为输入/输出匹配及级间匹配,以减小芯片的面积,从而降低成本。采用Cadence、ADS和Momentum等软件进行联合仿真。后仿真结果表明,在工作频段为60 GHz时,最大小信号增益为26 dB,最大功率附加效率为18.6%,饱和输出功率为15.2 dBm。该功率放大器具有高增益、高效率、低成本等优点。     

6?10 GHz ultra-wideband CMOS LNA

A two-stage matched ultra-wideband CMOS low noise amplifier (LNA) is presented. The LNA is designed to achieve a low noise figure with high voltage gain. The LNA fabricated in a 0.13 mum CMOS process shows a 3.9 dB average noise figure with a 27 dB voltage gain in the 6-10 GHz frequency band with a power consumption of 14 mW.