用SiH_4-NH_3体系减压化学汽相淀积氮化硅薄膜的工艺研究

近些年来,使用扩散炉由减压方式产生的化学汽相淀积技术(简称LPCVD技术),在一些技术发达的国家中已有很大的突破和进展,国内对这项技术也引起了极大的重视,并且取得了较快的进展。LPCVD技术所以能被迅速的接受,是由于它采用密集垂直装片方式,生产量大,效率高。同时,它在一个固定的电阻炉内硅片直接受热,在低压下可以导致淀积非常均匀的薄膜厚度和组份。 采用LPCVD技术淀积多晶硅、氮化硅、二氧化硅和磷硅玻璃等薄膜,近些年国外不断有所报导。表1列出了各种淀积膜的现状。 近两年来用LPCVD技术淀积多晶硅、氮化硅薄膜国内也有些报导。特别是LPCVD多晶硅报导的较多,进展较显著,问题点也不多。而LPCVD氮化硅薄膜与多晶硅比较,生长     

多晶硅膜的结构及其性质分析

本文主要叙述低压化学汽相淀积(LPCVD)多晶硅膜的生长机构、多晶硅膜结构、淀积温度与多晶硅膜结构的关系、影响膜层质量的主要因素、引起膜表面“发雾”的原因以及膜的性质。     

LPCVD多晶硅薄膜发雾的形成与消除

LPCVD多晶硅薄膜发雾对CMOS器件性能有重大影响,文章分析了多晶硅薄膜发雾的形成机理与影响因素,指出了低温、低压以及保持气路系统的清洁是消除多晶"发雾"的有效措施。根据多晶硅薄膜雾状斑点的形状与分布位置,对硅片表面缺陷的来源进行了分类,并从清洗工艺、污染物成分分析、前道工序等方面提出了相应的解决措施。     

掺氧多晶硅(SIPOS)薄膜结晶学性质研究

本文用XRD,RHEED和SEM对LPCVD掺氧多晶硅的结晶学性质进行了研究.结果表明,对于含氧量为8～37at%预淀积SIPOS薄膜其结构呈无定形.当进行高温热退火(T_a≥900℃)时,薄膜经历了一个再结晶过程.晶粒度的大小与退火条件有关;而修氧多晶硅中的含氧量对再结晶过程具有抑制作用.     

LPCVD掺氧多晶硅薄膜淀积及其特性

本文对LPCVD掺氧多晶硅的工艺特性进行了研究,尤其是分析和讨论了在LPCVD系统中淀积温度、反应气体流量比(N_2O/SiH_4)及硅烷(SiH_4)流量对SIPOS薄膜的工艺参数及薄膜性质的影响,并对LPCVD-SIPOS的有关性质进行了讨论。     

低压化学汽相沉积多晶硅工艺

本文介绍我所自制低压化学汽相沉积设备生长多晶硅工艺情况。通过实验摸索及流水线试片表明,LPCVD反应器生长多晶硅具有成本低、产量大、薄膜均匀及洁静度高等优点。此外,不用携带气体,工艺简单。我们采用20％的氦气稀释的硅烷,系统压力在0.5乇到1乇下进行淀积,淀积温度为580℃～680℃之间,硅烷流量在200～225cc/分。生长的多晶硅膜厚度为2000～8000,其淀积速率为30～280/分。根据电子扫描显微镜对晶粒的研究表明,晶粒比常压生长的晶粒要小些;晶粒大小随淀积温度增加而增加;同时方块电阻也随淀积温度增加而下降;随膜厚增加方块电阻减小。     

LPCVD多晶硅膜的制备和在硅化铂肖特基势垒红外电荷耦合器件(PtSi-SBIRCCD)中的应用

本文介绍热壁低压化学汽相淀积(LPCVD)制备多晶硅膜的淀积变量,影响膜层质量的因素。其次简述了多晶硅膜的等离子刻蚀情况及其在硅化铂肖特基势垒红外电荷耦合器件(Ptsi-SBIRCCD)研制中的应用。     

三个微加工可变电容式马达的研究

本文讨论了三种可变电容式电动马达的工作原理、设计和微细加工.它们分别是顶部驱动式、侧向驱动式和调谐侧向驱动式三种.这些微型马达的各自优点与不足之处也一并作了讨论.本文中讨论的这些微型马达都是通过表面微细加工的方式制得的.高掺杂的LPCVD多晶硅用作结构部分,牺牲层采用LPCVD氧化硅,而LPCVD氮化硅用作电绝缘.整个加工过程包括两次多晶硅淀积,两次氧化硅及两次氮化硅淀积等步骤.     

OLD诊断SiH_4的LPCVD动力学过程

用光声激光偏转(OLD)测量了强TEA CO_2脉冲激光辐照SiH_4-H_2系统产生等离子体淀积(LPCVD)硅薄膜过程中的激波效应,证明激光击穿SiH_4诱发的激波效应是LPCVD中基本的气体动力学过程,并讨论了激波对膜生长的影响。     

热壁LPCVD多晶硅膜的质量分析

对就热壁ＬＰＣＶＤ多晶硅的基本原理、典型淀积条件、掺杂、均匀性，引起多晶硅膜层表面“发乌”、“发雾”的原因和提高多晶硅膜质量的工艺措施作了分析和研究。     

Single-wafer polysilicon engineering for the improvement of over erase in a 0.18-/spl mu/m floating-gate flash memory

A new polysilicon grain engineering technology for the improvement of over erase in 0.18-/spl mu/m floating-gate flash memory has been developed with the use of single-wafer polysilicon processing, which makes it practical to use hydrogen as a process variable. The addition of hydrogen in polysilicon deposition significantly alters the reaction kinetics and produces polysilicon thin film of smooth surface, fine and uniformly distributed grains. Such a micrograin polysilicon possesses show excellent high-temperature stability. The benefits of the micrograin polysilicon are to be demonstrated through its improvement in over erase of a 0.18-/spl mu/m floating-gate flash memory.     

Influence of polysilicon film thickness on radiation response of advanced excimer laser annealed polycrystalline silicon thin film transistors

This paper presents results of gamma irradiation effects in advanced excimer laser annealed polysilicon thin film transistors realized in polysilicon films having different thicknesses. It is shown that the thickness of polysilicon film has a strong influence on the degradation level of electrical parameters of irradiated thin film transistors, offering a possibility for optimization of these devices with the purpose to increase their reliability. The analysis was performed by monitoring of important electrical parameters, as well as of the density of irradiation induced oxide trapped charge and interface traps at the oxide–polysilicon interface, and the density of polysilicon grain boundary traps in the channel region of the transistors.     

范德堡多晶硅热导率的测试结构

在O.M.Paul等研究的范德堡热导率测试结构的基础上,提出了一种改进结构,利用一组测试结构来测得多晶硅薄膜的热导率。在十字型结构中一个含有多晶硅薄膜,而另一个不含有多晶硅薄膜,根据建立的热学模型,可以获取多晶硅薄膜的热导率。用有限元分析软件ANSYS进行了模拟分析,分析表明模拟值与实验值能较好地吻合,且辐射散热是基本可以忽略的,从而验证了模型建立的正确性,说明该方法能够实现对多晶硅薄膜的测量,且具有较高的测试精确度。     

多晶硅薄膜热膨胀系数的电测试结构

提出了一种新型多晶硅薄膜热膨胀系数的电测试结构,给出了热机电耦合模型和测试方法,并利用Coventor软件和ANSYS软件进行模拟和验证.分析表明模拟结果和理论结果基本一致,从而验证了该模型.该方法能够实现多晶硅薄膜热膨胀系数的在线提取,测量方便,独立性较高,以电学量形式输出,对于薄膜热膨胀系数的在线检测有一定参考价值.     

多晶硅薄膜热膨胀系数的电测试结构

提出了一种新型多晶硅薄膜热膨胀系数的电测试结构,给出了热机电耦合模型和测试方法,并利用Coventor软件和ANSYS软件进行模拟和验证.分析表明模拟结果和理论结果基本一致,从而验证了该模型. 该方法能够实现多晶硅薄膜热膨胀系数的在线提取,测量方便,独立性较高,以电学量形式输出,对于薄膜热膨胀系数的在线检测有一定参考价值.     

A methodology for optimizing a constant temperature polysilicondeposition process

A three-step approach to characterizing a low pressure chemical vapor deposition (LPCVD) constant temperature polysilicon process is discussed. This approach optimizes an LPCVD polysilicon process for both film uniformity and particles. The first step is to design and construct a constant deposition temperature polysilicon furnace to provide the best system performance possible in terms of particle generation and improved film uniformity. The second step is to characterize a process in this newly constructed furnace for both film uniformity and particles by using an experimental design that incorporated an L₁₈ orthogonal array. The hydrogen chloride preclean flow prior to deposition plays a key role in both defect generation and film uniformity. Both capacitance-voltage techniques and secondary ion mass spectrometry are used to understand this role. The third step is to verify the recommended setting from the experimental design by processing confirmation runs. Results from the confirmation runs in the optimally constructed polysilicon furnace show that particles can be reduced by up to 66% and film uniformity can be improved by 29% over the current production process     

Fabrication of thick films of silicon-on-insulator substrates by using a scanning halogen lamp system

A technique for preparing thick films of silicon-on-insulating substrates is presented. We start with a classical deposition of a thin film of polysilicon on patterned stripes of SiO2 grown on Si wafers. The energy of the focused light of a halogen lamp induces a deep melting in the upper part of the substrate. This results in a controlled sinking of the SiO2 strips in the molten silicon. By scanning the molten zone, the silicon solidifies at the leading edge, and the resulting film is made of 20?40 ?m-thick stripes of defect-free Si-on-SiO2 separated by seeding areas.     

Silicon nano-asperities: Morphological evolution and electrical properties of double-polysilicon interlayers

Polysilicon/silicon-dioxide/polysilicon structures (double polysilicon) are grown by deposition of amorphous silicon followed by thermal oxidation and a final polysilicon deposition process. Correlation between the appearance of silicon nano-structures and surface morphology formed during the amorphous silicon deposition stage and the electrical characteristics of the double poly capacitor have been investigated. It is shown that the process parameters have a pronounced effect on the morphological properties of the film surface. Nanometric size asperities form during the amorphous silicon deposition stage. The density and height distribution of these asperities were found to depend on deposition temperature. Thermal oxidation of the amorphous layer resulted in the growth of a top oxide layer and crystallization of the bottom silicon film. This process results in an overall increase of the surface roughness and a pronounced decrease in the height of the nano-asperities. By HF-etching the oxidized film, the surface of the polycrystalline silicon is exposed. Following this etching process, the surface roughness increases, whereas the density and height of the nano-asperities decrease. A correlation between the height of asperities on the bottom amorphous silicon film (as well as roughness of this film) and the breakdown voltage of the double poly was found.     

提高多晶电阻工艺稳定性

文章通过对多晶薄膜的性质和多晶电阻形成工艺的稳定性研究,剖析在生产过程中三种形成多晶电阻主要工艺的波动情况,并对形成工艺波动的原因和控制方法进行了讨论。同时对于采取控制方法以后的多晶电阻的工艺情况进行分析,证明提高多晶电阻制造工艺稳定性必须提高多晶淀积和离子注入工艺能力,以及如何提高多晶淀积和离子注入的受控。最后对采取控制措施后的多晶电阻的改善效果进行回顾,说明离子注入工艺采取除气和多晶淀积隔片放置方式有效地提高了多晶电阻工艺的稳定性。     

多晶硅薄膜的高温压阻效应

利用LPCVD制备重掺杂多晶硅薄膜,在0～560℃温度范围内对薄膜的压阻效应进行研究,同时对多晶硅薄膜应变系数随温度的变化,以及薄膜的淀积温度与薄膜厚度对应变系数的影响进行了相关的实验研究.结果表明,利用多晶硅材料制作的压敏电阻,其最高工作温度可以达到560℃以上.