DSP内嵌PLL中的CMOS压控环形振荡器设计

介绍了一种用于DSP内嵌锁相环的低功耗、高线性CMOS压控环形振荡器.电路采用四级延迟单元来获得相位相差90.的正交输出时钟,每级采用调节电流源大小,改变电容放电速度的方式.基于SMIC 0.35μm CMOS工艺模型的仿真结果表明,电路可实现2MHz至90MHz的频率调节范围,在中心频率附近具有很高的调节线性度,且总功耗仅为3.5mW.     

一种低相噪CMOS环形振荡器设计

设计了一种带有正交输出,频率为900MHz的两级低相噪环形振荡器,电路设计采用0.18μm CMOS工艺,电源电压为1.8V.环形振荡器的调谐范围随控制电压从0V的1460MHz到电源电压1.8V的720MHz发生变化,并且具有较好的线性度.在频率为900MHz、偏移载波频率为600kHz的情况下,环形振荡器的相位噪声为-108dBc/Hz,功耗为18mW.在与其它环形振荡器的比较中,yynw环形振荡器显示了较好的性能参数.     

一种低功耗交叉耦合环形振荡器

通过引入NMOS交叉耦合结构,设计了一种低功耗,低相位噪声的二级环形振荡器.采用TSMC 0.25μm CMOS工艺参数,用Cadence的Spectre软件进行仿真,在3.3V电压下,工作频率可达2G,偏离主频1MHz处相位噪声为-95.6dBc/Hz.功耗为3.2mW.     

一种具有低电源敏感度的高速CMOS压控振荡器

给出了一种低电源敏感度的高速CMOS压控振荡器设计,在延时单元中引入正反馈结构以补偿电源电压变化对输出频率的影响,在TSMC0.25μmCMOS工艺参数下使用Hspice仿真表明,电源变化1%引起的输出频率变化小于0.7%,整体振荡器的输出频率范围为2.01GHz-2.75GHz。     

Ku波段0.18μm CMOS压控振荡器电路设计

在TSMC 0.18μm RF CMOS工艺下设计了一个Ku波段电感电容压控振荡器,该电路采用NMOS交叉耦合型,结合滤波技术降低相位噪声,并利用开关电容阵列为其扩频,使电路获得卓越的性能。后仿真结果表明,该电路实现了10 GHz~14 GHz的宽调频,在整个频带内其相位噪声低于-112 dBc/Hz在1 MHz的偏移处;在1.8 V的电压下,核心电路工作电流为5 mA。     

一种射频接收芯片中的低相位噪声压控振荡器

本文介绍了一种适用于ASK幅移键控接收器芯片中锁相环电路,集成于芯片内的LC压控振荡器,它的LC振荡电路采用了一种增强型的特别结构。芯片采用锁相环电路来产生本振信号。接收器通过它工作在290MHz到470MHz的ISM频段。锁相环中的VCO采用了差分对结构的LC压控振荡器结构,在1V到5V的控制电压下能产生290到470的可调频率,输出功率为2.20到2.30dBm。该VCO采用了增强型结构的LC振荡电路以得到更高的Q值来减小相位噪声,采用这种特殊结构,它能在433MHz载波的100kHz偏移范围内实现-99.7dBc/Hz的相位噪声。与普通LC振荡电路结构相比,该结构能使VCO相位噪声减小3dBc以上。且由于该电路由较少的有源器件组成,因此该VCO有着非常低的功耗和成本。     

一种带有隔离技术的高频压控振荡器

提出一种带有谐振电路隔离技术的电感电容压控振荡器。该技术通过两个三极管将谐振电路和其它电路隔离,减少了谐振电路中等效电容的大小,进而增加了电感电容压控振荡器的振荡频率。提出的电感电容压控振荡器采用华虹NEC的0．181xmSiGeBiCMOS工艺,振荡频率达到12．35GHz。在其它性能相同的情况下,提出的电感电容压控振荡器的振荡频率比典型的电感电容压控振荡器的振荡频率高出20％以上。     

2．4GHz低相位噪声CMOS负阻LC压控振荡器设计

为了有效降低工作于射频段的全集成CMOS负阻LC压控振荡器的相位噪声．介绍了利用电阻电容滤波技术对振荡器相位噪声的优化,并采用Chartered 0．35μm CMOS标准工艺设计了一款全集成CMOS负阻LC压控振荡器,其中心频率为2.4GHz,频率调谐范围达到300MHz,在3．3V电压下工作时,静态电流为12mA,在偏离中心频率600kHz处,仿真得到的相位噪声为-121dBc／Hz。该设计有效地验证了电阻电容滤波技术对相位噪声的优化效果,并为全集成低相位噪声CMOS负阻LC压控振荡器的设计提供了一种参考电路。     

正交相位输出压控振荡器的低相位噪声优化设计

分析了负阻结构 LC 压控振荡器各组成部分对相位噪声的贡献途径及优化方法;介绍了利用两独立 VCO 核心输出正交相位信号的原理及其相位噪声优化方法;利用所得结论设计出工作于 ISM波段2.4GHz 的 QVCO,相位噪声在100kHz、1MHz 和3MHz 频偏处分别达到-103.3、-121.1和-125.9dBc/Hz,仅消耗功率3.8 mW;所设计电路利用 HJTC0.18μm工艺制造,占用芯片面积0.75mm×1mm。     

基于环形振荡器的压控振荡器的频率设计

文章分析了环形振荡器中延迟环节内与延迟时间(即振荡频率)有关的MOS管参数问题,结合一个中心频率为600MHz,0.18-μmCOMS制造工艺,1.8-V电源电压的VCO设计,做了仿真验证。最后文章总结出对于一般的基于环形振荡器的压控振荡器的频率调解的方法。     

Low power quadrature voltage controlled oscillator

In this article, a low voltage low power quadrature voltage controlled oscillator (QVCO) coupled by four P&N transistors is presented. First, a novel negative resistance inductance capacitor (LC) oscillator is described, the N‐metal oxide semiconductor (NMOS) and P‐metal oxide semiconductor (PMOS) transistors are in series with the LC tank in the direct‐current (DC) path, and they generate the required negative resistance to compensate the energy loss of the LC tank and maintain the steady oscillation of the oscillator. Then, based on two identical LC oscillators, four P&N transistors are used as coupling terminals to generate quadrature outputs. The proposed QVCO is designed and simulated with GlobalFoundries' 0.18 μm CMOS RF process. The Cadence IC design tools postlayout simulation results demonstrate that the oscillation frequency of the QVCO can be tuned from 2.0 to 5.6 GHz by adjusting the bias voltage, and the phase noise of the voltage controlled oscillator is ?114 dBc/Hz at 1 MHz offset. Moreover, the proposed QVCO consumes only 2.31 mW from a 1.2 V supply voltage and it occupies a compact area of 0.45 mm² including the bond pads.     

前馈环形振荡器的结构与相位噪声研究

基于高速串行通信系统中锁相环和时钟数据恢复电路的需求,研究了前馈环形振荡器的结构与工作原理;在传统结构的基础上,将前馈路径耦合至主路径反相器的源极,可以提高输出信号的边沿速率;最后基于Hajimiri模型的脉冲灵敏度函数进行分析,提出的结构有效降低了热噪声和闪烁噪声的引入.在28 nm CMOS工艺下设计了单源极前馈型...     

A low power and small area all digital delay-locked loop based on ring oscillator architecture

A 133-500 MHz,5.2 mW @500 MHz,0.021 mm2 all digital delay-locked loop(ADDLL)is presented.The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator(ROSC)to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed.The proposed ADDLL has better immunity to PVT(process,voltage,and temperature)than most conventional DLLs,which do not update the control word signals after the locking process,since the control signals for slave delay line are updated in every 256 reference cycles.Fabricated in 0.13 um CMOS process,the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.     

2.4GHz低相位噪声CMOS负阻LC压控振荡器设计

为了有效降低工作于射频段的全集成CIVICS负阻LC压控振荡器的相位噪声,介绍了利用电阻电容滤波技术对振荡器相位噪声的优化,并采用Chartered 0.35μm CMOS标准工艺设计了一款全集成CMOS负阻LC压控振荡器,其中心频率为2.4GHz,频率调谐范围达到300MHz,在3.3V电压下工作时,静态电流为12mA,在偏离中心频率600kHz处,仿真得到的相位噪声为-121dBc/Hz.该设计有效地验证了电阻电容滤波技术对相位噪声的优化效果,并为全集成低相位噪声CMOS负阻LC压控振荡器的设计提供了一种参考电路.     

A current‐mode tunable low‐supply‐voltage ring oscillator

A new circuit topology using a current‐mode low‐pass filter for sinusoids has been presented. The technique is relatively simple, in the proposed circuit, only three identical current‐mode low‐pass filters are connected to each other to realize the small signal path. No external passive components are required except for three capacitors. When compared with LC oscillators, the die area of this work, without inductors, is much smaller. When compared with voltage‐mode ring oscillators, the supply voltage of this work is much lower. As a particular example, a 2.4 GHz, 1.2‐V power supply, 5‐mW sinusoidal oscillator is demonstrated. The oscillation frequency is tuned by the value of that three capacitors, over ～900 MHz, and the tuning range is 37.5%. The phase noise results in ?94 and ?120 dBc/Hz at 1 and 10 MHz from the carrier, respectively. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010.     

An analytic method of microwave bipolar single‐frequency and voltage‐controlled oscillator design

An analytic method of microwave bipolar oscillator design, allowing one to define explicit expressions for optimum values of feedback elements and load through bipolar transistor Z‐parameters, is developed. A negative resistance concept is utilized to design series feedback microwave bipolar oscillator with optimized feedback elements and maximum output power in terms of the transistor impedance parameters. The design of the wideband common‐base bipolar voltage controlled oscillators (VCOs) is also presented. Numerical and experimental results verify the validity of the design methods described. ©1999 John Wiley & Sons, Inc. Int J RF and Microwave CAE 9: 403–414, 1999.     

2.42 GHz宽带低相噪LC压控振荡器的设计

采用一种基于开关电容阵列(SCA)和电压、电流滤波相结合的电路结构,设计了一个宽调谐范围低相位噪声的互补交叉耦合型LC压控振荡器。利用ADS仿真软件对电路进行仿真,达到了宽调谐、低相位噪声、低功耗的要求。     

一种低压低功耗的亚阈型CMOS基准电压源

介绍一种低压、低功耗和低温度系数CMOS基准电压源,该基准电压源的核心MOSFET工作在亚阈值区,采用亚阈值型MOSFET低于某个特定偏置点时,具有负温度系数的特点.电路用标准的0.35 μm CMOS工艺设计,在-40℃～+110℃范围的温度系数为262.6 ppm/ ℃时,基准的输出电压为345.36 mV.本文也...