Distortion in single-, two- and three-stage amplifiers

Nonlinear distortion in single-, two-, and three-stage operational amplifiers (opamps) is the main scope of this paper. For each opamp, distortion contributions from different groups of transistors are identified and plotted versus frequency. This makes it possible to find the strongest sources of distortion in the various frequency regions. Further, equations that describe the third harmonic as a function of circuit parameters and input frequency are presented. Despite the simplifications, these equations describe the third harmonic accurately. Further, they provide insight and understanding by connecting distortion to circuit parameters such as transconductances, capacitances, poles, and zeros. The comparison of the opamps shows that each opamp has a frequency region where the distortion is lower than for the other two. The three-stage op amp has far lower distortion at low frequencies, the single-stage op amp is better at high frequency and the two-stage op amp is best for the mid frequency range.     

Modified Model for Settling Behavior of Operational Amplifiers in Nanoscale CMOS

An accurate time-domain model for the settling behavior of folded-cascode operational amplifiers is presented. Using a velocity–saturation model for MOS transistors makes the proposed model suitable for nanoscale CMOS technologies. Both linear and nonlinear settling regimes and their combination are considered. Transistor-level HSPICE simulation results of a fully differential single-stage folded-cascode amplifier using BSIM4v3 models of a standard 90-nm CMOS process are presented to verify the accuracy of the proposed models.      

Design of a low EMI susceptibility CMOS transimpedance operational amplifier

In this work we analyze the effects of electromagnetic-induced interferences conveyed at the input of a transimpedance CMOS operational amplifier. In particular, it will be highlighted that transimpedance amplifiers natural exhibit a lower EMI susceptibility compared to common voltage-feedback opamps. Moreover, it will be shown through simulations that a careful circuit design can lead to opamps with a practically vanishing EMI susceptibility.     

Design of an Operational Amplifier Input Stage Immune to EMI

This paper presents a new analytical model to predict upsets, which are induced by electromagnetic interferences (EMI) in CMOS operational amplifiers (opamps). In particular, it is pointed out that the demodulation of EMI, which is experienced in feedback CMOS opamps, is related to the power spectral density of the interfering signals reaching the opamp input terminals. Furthermore, the new model is employed to design a differential stage immune to EMI.     

Design of SOI CMOS operational amplifiers for applications up to300°C

Design guidelines using two analog parameters (Early voltage and transconductance to drain current ratio) are proposed for correct operation of silicon-on-insulator (SOI) CMOS operational amplifiers (opamp) at elevated temperature up to 300°C. The dependence of these parameters on temperature is first described. A new single-stage CMOS opamp model using only these two parameters is presented and compared to measurements of several implementations operating up to 300°C for applications such as micropower (below 4 μW at 1.2 V supply voltage), high gain (65 dB) or high frequency up to 100 MHz. Trade-offs among such factors as gain, bandwidth, phase margin, signal swing, noise, matching, slew rate and power consumption are described. The extension to other architectures is suggested and the design methodology is valid for bulk as well as SOI CMOS opamps     

A novel class of complementary folded-cascode opamps for low voltage

Three novel complementary folded-cascode operational amplifiers (opamps) with high gain, large bandwidth, and rail-to-rail input range for low-voltage operation will be presented. These opamps feature high bandwidth due to minimum internal nodes. The output swing is increased by properly adjusting the output cascode transistor gate voltages close to the power supply voltages. The opamps have been fabricated with a standard 0.8-/spl mu/m CMOS technology. Measurements show the amplification is between 60.1 and 72.4 dB, and the unity gain bandwidth is 14 MHz for a 5-pF load, 2.5-V power supply, and 150-/spl mu/A bias current.     

Summing proportioning absolute value circuit

An absolute value circuit is presented that provides the absolute value of a weighted sum of several inputs. In contrast to previous realizations, which required three operational amplifiers, only two opamps are required.     

Design, measurement and analysis of CMOS polysilicon TFToperational amplifiers

The small signal properties of polysilicon TFT opamps have been investigated in this paper. A method for the scaling of g_m (transconductance) and g_ds (output conductance) has been proposed, facilitating their estimates for various transistors in operational amplifiers. The analysis of two CMOS opamps fabricated by a low temperature, glass compatible poly-Si TFT process is demonstrated in comparison to the measured performance. The first implementation has been internally compensated with high load-driving capability (up to 36 pF), while the second one has employed a cascode stage for increased gain (56 dB)     

Four-quadrant analogue multiplier using operational amplifier

A method to realise a four-quadrant analogue multiplier using general-purpose operational amplifiers (opamps) as only the active elements is described in this article. The realisation method is based on the quarter-square technique, which utilises the inherent square-law characteristic of class AB output stage of the opamp. The multiplier can be achieved from the proposed structure with using either bipolar or complementary metal-oxide-semiconductor (CMOS) opamps. The operation principle of the proposed multiplier has been confirmed by PSPICE analogue simulation program. Simulation results reveal that the principle of proposed scheme provides an adequate performance for a four-quadrant analogue multiplier. Experimental implementations of the proposed multiplier using bipolar and CMOS opamps are performed to verify the circuit performances. Measured results of the experimental proposed schemes based on the use of bipolar and CMOS opamps with supply voltage ±2.4 V show the worst-case relative errors of 0.32% and 0.47%, and the total harmonic distortions of 0.47% and 0.98%, respectively.     

Finite common-mode rejection in fully differential operational amplifiers

A nonlinear mechanism which affects common-mode rejection (CMR) of fully differential integrated operational amplifiers (opamps) is highlighted and analysed by computer simulations. In particular, it is shown how the finite CMR of fully differential opamp circuits under practical operating conditions is mainly related to such a mechanism rather than to transistor mismatch.     

Low-noise two-wired buffer electrodes for bioelectric amplifiers

Active buffer electrodes are known to improve the immunity of bioelectric recordings against power line interferences. A survey of published work reveals that buffer electrodes are almost exclusively designed using operational amplifiers (opamps). In this paper, we discuss the advantage of utilizing a single transistor instead. This allows for a simple electrode, which is small and requires only two wires. In addition, a single transistor adds considerably less noise when compared to an opamp with the same power consumption. We then discuss output resistance and gain as well as their respective effect on the common mode rejection ratio (CMRR). Finally, we demonstrate the use of two-wired buffer electrodes for a bioelectric amplifier.     

Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters

Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology.     

Relationship between frequency response and settling time of operational amplifiers

The effects of pole-zero pairs (doublets) on the frequency response and settling time of operational amplifiers are explored using analytical techniques and computer simulation. It is shown that doublets which produce only minor changes in circuit frequency response can produce major changes in settling time. The importance of doublet spacing and frequency are examined. It is shown that settling time always improves as doublet spacing is reduced whereas the effect of doublet frequency is different for 0.1 and 0.01 percent error bands. Finally it is shown that simple analytical formulas can be used to estimate the influence of frequency doublets on amplifier settling time.     

Design of integrated BiCMOS operational amplifiers with low-probability EMI-induced-failures

Electromagnetic interference may cause failures in operational amplifiers. The probability of these failures can be reduced by properly designing the opamp, once the failure mechanism has been discovered. In this paper the design of some integrated BiCMOS operational amplifiers with a very low-probability of electromagnetic interference (EMI) induced failures is reported. In particular, it is shown that opamps exhibiting good general performances as well as low EMI-susceptibility can be obtained only if their response to a large square-wave input signal is symmetric and the influence of some parasitic capacitances in the input stage is compensated. Following these guide-lines, we found possible to design BiCMOS opamp structures exhibiting EMI susceptibility of only a few mV up to several hundred MHz when they are driven with an interfering input signal of some volts.     

Failures induced on analog integrated circuits by conveyed electromagnetic interferences: A review

Failures induced on analog integrated circuits by electromagnetic interference (EMI) will be analyzed with particular emphasis on integrated operational amplifiers built with different technologies. Additionally, the correlation found between EMI susceptibility and large-signal opamp behavior will be discussed. Some criteria for the design of low EMI susceptibility opamps will be derived. Finally, as an application example, the design of a BiCMOS opamp with an extremely low-probability EMI-induced failure will be presented.     

A new current-differencing single-supply operational amplifier

The conventional integrated-circuit operational amplifier is not well suited to many system applications that operate from only a single power supply voltage. To more optimally meet the requirements of industrial control systems a new current- differencing opamp has been developed that uses a simple circuit to provide a gain element that out performs the 741 IC opamp. As a result of the circuit simplicity, multiple opamps are possible and six independent internally compensated amplifiers have been fabricated on a single 80/spl times/93-mil die. Many circuits are presented only not to show how this circuit can perform most the application functions of a standard IC opamp, but also to indicate the increased usefulness of this new input current differencing type of opamp circuit in single power-supply control system applications.     

Rail-to-rail super class AB CMOS operational amplifiers

Novel class AB single-stage operational amplifiers are presented. They feature rail-to-rail operation owing to the use of floating-gate input transistors. Initial charge of the floating gates is removed during fabrication, without any post-processing. The amplifiers are fast, simple, and able to operate at low supply voltages. They are highly power efficient owing to the enhanced (super) class AB operation based on adaptive biasing and local common-mode feedback. A 0.5 /spl mu/m CMOS implementation shows rail-to-rail operation with slew rates of about 40 V//spl mu/s for a load of 80 pF and 144 /spl mu/W of quiescent power consumption.     

Class of floating, generalised, positive/negative immittanceconvertors/inverters realised with operational mirrored amplifiers

Through a systematic formulation based on nullors, a class of eight generalised positive/negative floating impedance (FI) configurations, realisable with four operational mirrored amplifiers (OMAs) and only three passive elements, is derived. The advantages offered by the proposed configurations are not simultaneously available in any of the previously known FI configurations employing opamps, current conveyors or OMAs. The feasibility of the new formulations together with some of their applications, have been confirmed by SPICE simulations     

Exact design for the settling time of two-stage Miller compensated operational amplifiers

Analog Integrated Circuits and Signal Processing - Most of the currently existed settling time design methods for the Miller-compensated two-stage operational amplifiers are based on the...     

Wideband CMOS Amplifier Design: Time-Domain Considerations

Time-domain responses of wideband CMOS amplifiers using several inductive peaking techniques are presented. Transient performance considerations are described, including the effects of transistor parasitics on settling and edge rates. A combination of time- and frequency-domain performance is derived for a given bandwidth extension technique, and tradeoffs are discussed. Measured results for several high-speed high-gain single-stage amplifiers are presented in 0.18-$mu$m CMOS, and a design strategy for multistage amplifiers is introduced. Finally, design and simulation results are presented for a multistage amplifier in 0.18-$mu$m CMOS that attains a bandwidth of 22.7 GHz with 14.7-dB voltage gain, operates at 40 Gb/s, and consumes 93.6 $~$mW.