A deep-submicrometer microwave/digital CMOS/SOS technology

0.35-μm complementary metal-oxide-semiconductor (CMOS)/silicon-on-sapphire (SOS) n- and p-channel MOSFETs with a metal-over-polysilicon T-gate structure for monolithic microwave integrated circuit (MMIC) and digital applications are reported. The measured values for the current-gain cutoff frequency f_T were ⩾20 GHz for both n-channel and p-channel devices, and the values for the unilateral power-gain cutoff frequency f_max were 37 GHz for the p-channel and 53 GHz for the n-channel MOSFETs. The low effective resistance of the T-gate structure contributed to the very high f_max values. It is believed that these are the highest f_T and f_max values ever reported for MOS devices. The potential of SOS submicrometer MOSFETs for microwave circuit applications is demonstrated     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

High-frequency InP/InGaAs double heterojunction bipolar transistorson Si substrate

Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I_C=15 mA, f _T was 59 GHz at V_CE=1.8 V, and f _max was 69 GHz at V_CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V_CE of 3.8 V was applied for I_C=7.5 mA in the S-parameter measurements to give an f_T of 39 GHz and an f_max of 52 GHz     

An NMOS input merged bipolar/sidewall-MOS transistor with a bypasssidewall MOS transistor (NBiBMOS transistor)

The concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (V_CE or V_DE) is less than the turn-on voltage of the n-p-n bipolar transistor (V_BE=~0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy ~1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased     

A latch-up-like new failure mechanism for high-density CMOS dynamicRAMs

A latch-up-like failure phenomenon that shows hysteresis in the V_cc-I_cc characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is discussed. This failure is caused by large substrate-current generation due to the depletion-mode threshold voltage of n-channel transistors at near-zero substrate-bias operation. It is increasingly important not only to design a powerful substrate-bias generator but also to suppress the back-gate bias effect on the n-channel transistor     

Short-channel pMOSTs in a high-resistivity silicon substrate. II.Noise performance

For pt.I, see ibid., vol.39, no.10, p.2268-77 (1992). The noise performance, important for the use of p-channel transistors on high-resistivity silicon in analog applications, is investigated. This is done for the two operation modes: bulk (|V_gs|<|V_T|) and surface (| V_gs|>|V_T|). For the studied transistors, both modes are characterized by a 1/f noise spectrum extending to frequencies of up to ≈100 Hz, and followed by a white-noise spectrum, determined by the substrate resistance     

Consistent model for the hot-carrier degradation in n-channel andp-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V_g≈V_t) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model     

The complementary insulated-gate bipolar transistor (CIGBT)-a newpower switching device

A new power switching device, the complementary insulated-gate bipolar transistor (CIGBT), is described. The device achieves very high switching speeds typical of DMOS transistors, while it maintains the low on-state resistance of the insulated-gate bipolar transistor (IGBT) on which it is based. The device incorporates a p-channel MOS transistor which acts to draw excess charge out of the base region of the IGBT as the device is turned off. Fabricated devices whose specific on-resistance is only 20% greater than that of equal-area IGBTs display turn-off times under 700 ns, while the IGBTs require 35 μs to reach the off state. The device is compared to equal-area IGBTs, DMOS transistors, and IGBTs whose minority-carrier lifetime has been reduced to achieve 700-ns turn-off times     

Latchup-free Schottky-barrier CMOS

A common failure mechanism in bulk CMOS integrated circuits is due to the latchup of the parasitic SCR structure. Using Schottky-barrier junctions for the source and drain of the p-channel transistors eliminates the p-n-p-n structure. A technology utilizing platinum-silicide p-channel source and drain and ion-implanted n-channel source and drain was realized demonstrating latchup resistance without many sacrifices inherent with other methods. Anomalies in the p-MOSFET characteristics are reported and discussed.     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

Multigigahertz CMOS dual-modulus prescaler IC

A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes simultaneously the characteristics of both the p-channel and n-channel transistors for low-power-supply-voltage operation. Two different gate oxide thicknesses of 175 and 100 Å have been used. The best prescalar fabricated with 175-Å gate oxide functions at 2.06 GHz with 25-m W power consumption (L_eff=0.5 μm; V_dd=3.5 V). Preliminary results for prescalars fabricated with 100-Å gate oxide show that 4.2-GHz operation is possible (L_eff=0.4 μm; V _dd=3.5 V). Power-supply voltage as low as 1.7 V can be used for the prescalar to function at 1 GHz with a power consumption of only 4 mW     

Leakage-current-induced hot-carrier degradation of p-channelMOSFETs

Leakage-current-induced hot-carrier effects have been observed during stressing of p-channel MOSFETs in the OFF state with V _GS>0 V and V_DS<0 V. This mode of stressing results in increased leakage current and a positive shift in the value of V_GS, corresponding to the onset of avalanche breakdown of the drain junction. These effects are related to generation of interface states near the drain in forward-mode operation. By comparison, conventional stressing in the ON state with V _GS<0 V and V_DS<0 V resulted in little change in these p-channel MOSFET characteristics     

A self-aligned short process for insulated-gate bipolar transistors

An n-channel vertical insulated-gate bipolar transistor (IGBT) process which implements a self-aligned p⁺ short inside the DMOS diffusion windows is proposed and demonstrated experimentally. The salient feature of the new process is the placement of a poly-Si plug to define the diffusion window of the p⁺ short. Similar forward conduction characteristics and tradeoffs with turn-off time were obtained for these self-aligned short IGBTs when compared to conventional IGBTs with non-self-aligned shorts. With a resistive load and no external gate resistor, dynamic latching current was seen to increase with increasing p⁺ diffusion depth and electron irradiation dosage, as well as with larger p⁺ diffusion windows     

AlGaAs/GaAs double-heterostructure-emitter bipolar transistor(DHEBT)

An AlGaAs/GaAs double-heterostructure-emitter bipolar transistor (DHEBT) fabricated by molecular beam epitaxy (MBE) is presented. The use of a structure symmetrical with respect to the base layer results in bidirectional transistor and switching behavior. Due to a significant area difference between emitter-base and base-collector junction, an asymmetrical property is observed. With an emitter edge-thinning design, the transistor performance may be further improved. A common-emitter current gain of up to 140 with a negligible collector-emitter offset voltage (~40 mV) is achieved. A bidirectional S-shaped negative-differential-resistance (NDA) phenomenon occurs at high V _CE bias voltage. The temperature dependence of the NDR is investigated. A three-terminal-controlled switching device is found to perform well when the control current is introduced into the base electrode     

CW measurement of HBT thermal resistance

Measurements of the temperature dependence of β and V_BE were made on AlGaAs-GaAs HBTs and used to determine device thermal resistance. The measurements were CW and not switched or pulsed in order to have a simpler procedure. With base doping greater than 10¹⁹ cm^-3, HBTs have negligible base-width modulation (i.e., flat I_C versus V_CE characteristics) which makes CW thermal resistance measurement especially direct and simple     

Measurements and modeling of the n-channel MOSFET inversion layermobility and device characteristics in the temperature range 60-300 K

Discussed is the use of the high-frequency split C-V method to measure accurately the effective mobility of the n-channel MOS transistor as a function of temperature, bulk charge Q _b, and inversion layer charge Q_i. The experimental data for Q_b and Q_i were verified by comparison with the results of numerical simulation. The results of the measurements were used to develop the mobility model, which is accurate in the 60-300 K temperature range. The proposed mobility model incorporates Coulombic, lattice, and surface roughness scattering modes and generalizes the previous model, which was limited to low-temperature operation of the MOSFET. The deviation from the universal (for different back biases) μ(E_eff) dependence, which becomes more pronounced at low temperatures and low E_eff, is included in the model and can be associated with the Coulomb scattering mechanism. The proposed model is verified by comparison of experimental data and simulated MOSFET I-V characteristics for different temperatures     

Thermal stability and secondary breakdown in planar power MOSFET's

The destructive secondary-breakdown mechanism of high-voltage n-channel power MOSFET's is discussed. A model is proposed in which the secondary breakdown is caused primarily by the negative-resistance effects of a parasitic bipolar transistor structure. The model suggests that destructive breakdown can be suppressed by a new no-surface-breakdown structure fabricated on a p^-on p⁺epitaxial wafer. Power MOSFET's having this structure have been realized and are completely free from secondary breakdowns, as suggested by the model. In addition, experimental evidence for excellent thermal stability of the power MOSFET is given by infrared scanner measurements of the temperature rise in the chip compared with bipolar transistors. An n-channel planar power MOSFET with a 400-W power limitation at 220-V breakdown voltage and a maximum current of 12 A has been successfully fabricated.     

Circuit performance of CMOS technologies with silicon dioxide andreoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO₂) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V_GS⩽5 V and B_DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO₂ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μ_p (hole mobility) of RONO p-channel devices. At 300 K, μ_p(RONO) is 14-8% smaller than μ_p(SiO₂) over the entire range of gate biases, while μ_n(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ_n(SiO₂) and reaches only 96% of μ_n(SiO₂) at V_GS=5 V. At 100 K, μ_n(RONO)/μ_n (SiO₂) at V_GS=5 V is increased to 1.10, however, μ_p(RONO)/μ_p(SiO₂) at V_GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO₂ inverters     

An anisotype GaAs/InxGa1-xAs heterojunctionfield-effect transistor for digital logic applications

An anisotype heterojunction field-effect transistor (A-HJFET) for GaAs digital integrated circuit applications is proposed. A thin, highly doped, strained In_xGa_1-xAs (x⩽0.2) n-channel is employed for improved transconductance while a p⁺-GaAs cap is used to enhance the dynamic gate voltage range of the device. Prototype devices with 5-μm gate lengths show a maximum transconductance of 80 mS/mm at V_ds=2 V and a forward gate bias voltage of up to +2 V without significant leakage current     

12-kV p-Channel IGBTs With Low On-Resistance in 4H-SiC

SiC bipolar devices are favored over SiC unipolar devices for applications requiring breakdown voltage in excess of 10 kV. We have designed and fabricated p-channel insulated-gate bipolar transistors (IGBTs) in 4H-SiC with 12-kV blocking voltage for high-power applications. A differential on-resistance of 18.6 $hbox{m}Omegacdothbox{cm}^{2}$ was achieved with a gate bias of 16 V, corresponding to a forward voltage drop of 5.3 V at 100 $ hbox{A/cm}^{2}$, indicating strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintaining a high carrier lifetime for conductivity modulation. The p-channel IGBT (p-IGBT) exhibits a transconductance that is $hbox{3}times$ higher than that of the 12-kV n-channel SiC IGBTs. An inductive switching test was done at 1.5 kV and 0.55 A $(sim !!hbox{140} hbox{A/cm}^{2})$ for the p-IGBTs, and a turn-on time of 40 ns and a turn-off time of $sim !!hbox{2.8} muhbox{s}$ were measured.