共查询到19条相似文献,搜索用时 93 毫秒
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介绍采用多微处理器所构成的分布式计算机系统。来完成某工程任务所要完成的多路信号产生系统,该系统每个产生信号子系统都有一个微处理器,这些微处理器通过紧耦合的互连方式来构成整个系统。本文主要介绍这种系统的设计思想。 相似文献
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介绍了利用4片ADSP21160构造的高速雷达信号处理器,并探讨了由链路口构成的松耦合多处理器系统,实现了雷达信号处理器对目标定位和搜索的MUSIC算法,通过研究高效并行处理技术和高速可靠的数据传输方法,确保了MUSIC算法的可行性和实时性。此多处理器系统已成功应用到了某雷达信号处理系统当中。 相似文献
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本文介绍了TD-SCDMA与McWill的特点与发展状况,提出了两者紧耦合的构想,设计了两者紧耦合互连的结构框架、两者紧耦合互连所用的标准协议与特定协议. 相似文献
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一种雷达信号处理系统新体系结构的设计 总被引:2,自引:2,他引:0
为了适应雷达信号处理大带宽的要求 ,现代雷达信号处理系统结构中广泛采用了基于开关的、点对点的互连结构。基于互连开关结构的信号处理系统具有可扩展性好、性能优越、成本较低的优点。由于采用低电压差分传输 ,在交叉开关之间的数据传输速率可以达到G比特 ,它成为今后先进雷达信号处理系统发展的方向。依据RapidIO互连协议规范 ,文中提出了基于多数字信号处理器和开关互连的雷达信号处理系统体系结构 ,并对其中的交叉开关模型及其性能进行了分析 ,最后对该信号处理系统的软件和硬件实现方法进行了讨论。 相似文献
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WLAN作为一种无线接入方式,是3G接入技术的一种补充,能为3G用户提供高速稳定的数据业务,因此二者间的互连受到了世界范围内的关注.文章从互连位置的选择出发,总结了主流的紧耦合、网关和松耦合方案.简要介绍了目前3GPP的提议方案,并就各个方案的优缺点进行了比较. 相似文献
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WLAN作为一种无线接入方式,是3G接入技术的一种补充,能为3G用户提供高速稳定的数据业务,因此二者间的互连受到了世界范围内的关注。文章从互连位置的选择出发,总结了主流的紧耦合、网关和松耦合方案。简要介绍了目前3GPP的提议方案,并就各个方案的优缺点进行了比较。 相似文献
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一种基于标准CMOS工艺的单片光互连 总被引:2,自引:2,他引:0
探索了采用标准CMOS工艺实现单片光互连的可行性。采用特许(Chartered)半导体公司3.3V、0.35μm标准模拟CMOS工艺设计并制造了一种单片光互连系统,并用两种结构研究了衬底噪声耦合对互连性能的影响。测试结果表明:该光互连系统可工作于几×103Hz,验证了基于标准CMOS工艺的单片光互连系统是可行的。 相似文献
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采用周期调制技术,系统研究了线形和正三角形结构的三光纤耦合系统中光信号传输量子特性的差别。在紧束缚近似下,得到三光纤耦合系统中光信号传输的耦合模方程组,并对不同系统参数对一些重要量子现象的影响进行了仿真。仿真结果表明,结构不同会导致量子隧穿及相干隧穿破坏等量子特性的改变,从而影响光信号能量分布及震荡频率。研究结果对设计新型的光交叉连接器等光纤器件有指导意义。 相似文献
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Ge Zhou Yimo Zhang Wei Liu 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2000,88(6):856-863
In this paper, we discuss the optical fiber interconnection technologies applied in the two types of parallel processing systems: 1) a backplane interconnection in a parallel processor array system and 2) a computing cluster network. We have set up a parallel processor array system using optical fiber to make point-to-point interconnection between processor elements and are developing a low-cost virtual parallel optical fiber interconnection link (VPOFLink) complying with peripheral component interconnect (PCI) local bus specifications for the computing cluster. VPOFLink is integrated with the popular PCI bus interface in order to make the link hold the same bandwidth as that of the PCI bus. It was fabricated as an available peripheral device that can been inserted into the bus slots of commercial computers directly and can operate under the control of PCI bus. Also in this paper, we demonstrate the optical fiber link for a ring network and the architecture of the ring network 相似文献
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介绍了一种基于高速串行总线的机载火控雷达可重构信号处理机的设计与实现,以及高速串行总线的技术优势,分析了机载火控雷达可重构并行信号处理机系统互连的需求,讨论了处理机的系统架构、串行总线协议、串行总线端点和链路管理器的设计实现和总线错误监测及处理方法。该处理机不仅有效解决了数据传输的瓶颈问题,而且实现了数据传输拓扑结构的可重构,提高了信号处理系统的灵活性和可靠性。 相似文献
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叙述一种使用ARM7处理器实现USB接口与CAN总线的方案,通过其可以在PC实现对CAN总线上设备的监控。系统的主控制器为NXP公司的ARM处理器LPC2119,内部集成两路独立的CAN控制器。USB接口采用沁恒电子的CH375。描述了USB-CAN通信接口工作的基本原理及CAN总线与USB之间的硬件接口电路。同时,分析了固件编程及使用通用I/O模拟并口读写时序方法。 相似文献
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《电子学报:英文版》2017,(6):1198-1205
FPGA based soft vector processing accelerators are used frequently to perform highly parallel data processing tasks. Since they are not able to implement complex control manipulations using software, most FPGA systems now incorporate either a soft processor or hard processor. A FPGA based AXI bus compatible vector accelerator architecture is proposed which utilises fully pipelined and heterogeneous ALU for performance, and microcoding is employed for reusability. The design is tested with several design examples in four different lane configurations. Compared with Central processing unit (CPU), Digital signal processor (DSP), Altera C2H tool and OpenCL SDK implementations, the vector processor improves on execution time and energy consumption by factors of up to 6.6 and 6.4 respectively. 相似文献
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I2C总线构成简单,使用灵活,被广泛应用于嵌入式产品设计。多片体积小、成本低的单片机作为主机共享总线并行处理,能够解决单机处理资源、实时性不足的问题,为复杂的应用需求提供了低成本高性能的解决方案。介绍了多主机系统硬件设计中布线和组合逻辑电平不同部分的方法,提出了一种解决总线竞争的软件方法并给出实现代码。 相似文献
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Mitsuo Ishii Hiroyuki Sato Morio Ikesaka Kouichi Murakami Hiroaki Ishihata 《The Journal of VLSI Signal Processing》1989,1(1):57-67
The general-purpose, highly parallel, cellular array processor (CAP) we developed features multiple-instruction stream, multiple-data stream (MIMD) processing and image display. Processor elements can number in several hundreds. The present system uses 256 processors. Each processor element consists of a general-purpose microprocessor, memory, and a special VLSI chip that performs parallel-processing-specific functions such as processor communication and synchronization. The VLSI has two 2M byte/s independent common bus interfaces for data broadcating and six 15M bit/s serial communication ports for local data communication. The chip also can process image data in real time for multiple processors. Use of the communication interfaces enables a variety of processor networks to be configured. One CAP application has been computer graphics, in which ray tracing is used to generate quality images. 相似文献
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A conductor layout technique is described that reduces nearest-neighbor crosstalk for multiconductor signal buses with applications in high-speed digital and microwave pulse integrated circuits. Periodic transposition of conductors in a bus increases the average spacing of formerly nearest neighbors and thus decreases their capacitive and inductive coupling compared with ordinary parallel conductors. A conductor transposition pattern is evaluated for crosstalk, propagation delay, and chip area. SPICE simulations demonstrate that conductor transposition reduces, in certain situations, near- and far-end nearest-neighbor crosstalk by roughly 40% compared with parallel conductors. Quantitative guidelines are developed for reducing nearest-neighbor crosstalk in a transposed five-conductor bus, including effects of signal rise time, source resistance, load capacitance, and bus length 相似文献