Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)

In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing technique that harnesses the inherent intraclock period interconnect idleness to implement wire sharing throughout the various hierarchical levels of design. It is illustrated in this paper that the WPM network can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Both, a system level analysis and circuit level verification of this WPM routing are presented in this paper. A multilevel interconnect network design simulator (MINDS) that uses system level interconnect prediction (SLIP) techniques and HSPICE circuit simulations for optimizing the interconnect dimensions has been used to assess the opportunities for application of WPM wire circuits in high performance digital designs. A custom routing example highlights the ease with which the WPM routing technique can be easily incorporated into the existing VLSI systems. In addition, for a 40 million transistor system case study, this system level analysis reveals that the use of a WPM network could result in an almost 20% decrease in the number of metal layers for less than 4% increase in dynamic power with no loss of communication throughput performance. The key virtues of WPM routing are its flexibility, robustness, implementation simplicity and its low overhead requirements.     

Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI)

For the first time, compact physical models are derived for crosstalk noise of coplanar resistance-inductance-capacitance lines in a gigascale integration (GSI) chip that simultaneously consider far and near aggressors in both the same metal level and distant metal levels. Since both the amplitude and duration of noise are important, the noise voltage-time integral can be defined as a figure-of-merit for crosstalk, and it is shown that this integral attains its maximum at the length at which the interconnect resistance becomes equal to twice the characteristic impedance. It is also shown that crosstalk can be prohibitively large if interconnects have small resistances. There is, therefore, a tradeoff between interconnect latency and crosstalk. The compact models are finally used to calculate the crosstalk noise voltage for the case that wire width is optimized by simultaneously maximizing data flux density and minimizing latency. It has been proven that by utilizing the optimal wire width for signal interconnects and twice of that for power and ground lines, the worst case peak crosstalk noise voltage becomes smaller than 0.25 V/sub dd/ for all generations of technology.     

Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)

Physical models are used to determine the ultimate potential performance of carbon nanotube interconnects and compare them with minimum-size copper wires implemented at various technology generations. Results offer important guidance regarding the nature of carbon nanotube technology development needed for improving interconnect performance. Since wave propagation is slow in a single nanotube, nanotube bundles with larger wave speeds must be used. At the 45-nm node (year 2010), the performance enhancement that can be achieved by using nanotube bundles is negligible, and at the 22-nm node (year 2016) it can be as large as 80%.     

Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI)

The supply voltage decrease and power density increase of future GSI chips demand accurate models for the IR-drop. Compact physical IR-drop models of on-chip power/ground distribution networks are derived for two generic types of packages. In the early stages of design, these models enable accurate estimates of all required power/ground grid interconnect dimensions and chip pad counts that are needed for power distribution. The models also quantify the tradeoff between on-chip interconnect dimensions and the number of I/O pads required for power distribution and therefore enable rigorous chip/package co-design. Comparison with SPICE simulations show less than 1% and 5% error for the wire-bond package and the flip-chip package, respectively.     

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

Sea of Leads (SoL) is an ultrahigh density (>10/sup 4//cm/sup 2/) compliant chip input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of SoL. SoL can lead to enhancements in reliability, electrical performance, manufacturing throughput, and cost. A chip with 12 /spl times/ 10/sup 3//cm/sup 2/ compliant I/O leads is demonstrated. The mechanically compliant I/O leads are designed to enable wafer-level testing and eliminate the need for underfill between chips and printed wiring boards by mitigating thermo-mechanical expansion mismatches between the two. The fabrication of partially nonadherent, or slippery, leads is desirable as it allows the leads to freely undergo strain during thermal cycling. Compared to adherent metal leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Microindentation experiments show that a polymer film with embedded air gaps provides substantially higher compliance than a polymer film without embedded air gaps.     

A stochastic wire-length distribution for gigascale integration(GSI). I. Derivation and validation

Based on Rent's Rule, a well-established empirical relationship, a rigorous derivation of a complete wire-length distribution for on-chip random logic networks is performed. This distribution is compared to actual wire-length distributions for modern microprocessors, and a methodology to calculate the wire-length distribution for future gigascale integration (GSI) products is proposed     

A stochastic wire-length distribution for gigascale integration(GSI). II. Applications to clock frequency, power dissipation, and chipsize estimation

For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size     

A minimum total power methodology for projecting limits on CMOS GSI

A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact “transregional” MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling     

Impact of die-to-die and within-die parameter fluctuations on themaximum clock frequency distribution for gigascale integration

A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-μm microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3σ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations     

Optimal n-tier multilevel interconnect architectures for gigascaleintegration (GSI)

A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle time, power consumption or number of metal layers. The predictive capability of this methodology, which is based on a stochastic wiring distribution, provides insight into defining the process technology parameters for current and future generations of microprocessors and application-specific integrated circuits (ASICs). Using this methodology on an ASIC logic macrocell case study for the 100 nm technology generation, the optimized n-tier multilevel interconnect architecture reduces macrocell area by 32%, cycle time by 16% or number of wiring tracks required on the topmost tier by 62% compared to a conventional design where pitches are doubled for every successive pair of levels. A new repeater insertion methodology is also described that further enhances gigascale integration (GSI) system performance. By using repeaters, a further reduction of 70% in macrocell area, 18% in cycle time, 25% in number of metal levels or 44% in power dissipation is achieved, when compared to an n-tier design without repeaters. The key distinguishing feature of the methodology is its comprehensive framework that simultaneously solves two distinct problems-optimal wire sizing and wiring layer assignment-using independent constraints on maximum repeater area for efficient design space exploration to optimize the area, power, frequency, and metal levels of a GSI logic megacell     

Trends and limits in monolithic integration by increasing the diearea

The authors consider the limits on growing the die area, and argue that they are essentially economic. The discussion is in terms of a simple system-cost model. At a given defect density, the optimum die area is determined by the balance between reducing the assembly cost, achieved by growing the die to bring interconnects on chip, and reducing the scrapping cost, achieved by shrinking the die to reduce the amount of processed Si lost every time defects occur. The author's model accurately reproduces past trends, and predicts the die area which minimizes the cost of a system of given complexity. Extrapolation of present trends indicates that the economic advantage of growing the die may be exhausted at die areas of ~8-20 cm². Dice with such an area may be encountered by the year 2010, when fundamental limits on miniaturization are also anticipated     

Interconnect capacitance characterization using charge-injection-induced error-free (CIEF) charge-based capacitance measurement (CBCM)

In this work, we describe a novel operation of charge-injection-induced error-free charge-based capacitance measurement (CIEF CBCM) method. This method has the simplest test structure among various CBCM methods by using only one N/PMOS pair. CIEF CBCM has the advantage of being free from charge-injection-induced errors and of efficient layout area usage. It is very suitable for industrial applications for large amounts of accurate capacitance characterizations with a limited layout area. Besides, CIEF CBCM is also implemented for investigating the impact of floating dummy metal fills on interconnect capacitance directly from silicon data.     

Electromigration-induced integration limits on the future ULSI'sand the beneficial effects of lower operation temperatures

In recent logic ULSI's, the problem of device integration density has tended to be dominated by interconnection-related issues rather than transistor-related ones. In seeking to establish an analytical model, this paper describes the limit on integration density caused by electromigration (EM) tolerance. In our model, all signal lines within a logic block are assumed to be local interconnections and to be the predominant factor in integration density. Also in our model, integration density is approximated to be inversely proportional to the average width of signal lines, which can be derived from their width distribution. The width distribution of EM-limited interconnections is connected to the gate width distribution of their corresponding driving transistors. The relation between the two distributions is derived by incorporating an expanded EM model that treats currents in signal lines as bi-directional periodic pulses. Scaling theory is also incorporated to investigate the future trend in integration density in terms of the MOSFET gate length. Calculated results predict that EM tolerance could become a significant restraining factor on the trend toward increasing integration density when MOSFET gate lengths are scaled down to the quarter-micron range. This constraint is found to disappear at moderately lower operation temperatures     

薄膜高密度互连技术及其应用

高密度互连(HDI)基片在微电子集成技术中用来缩小尺寸、减轻重量和提高电气性能。薄膜技术是获得高密度互连的最佳技术。文章介绍了薄膜高密度互连技术的概念、特点、设计与工艺考虑,并指出其主要领域的应用情况。     

超深亚微米高速互连的信号串扰研究

探讨了超深亚微米设计中的高速互连线串扰产生机制,提出了一种描述高速互连串扰的电容、电感耦合模型,通过频域变换方法对模型的有效性进行了理论分析。针对0.18μm工艺条件提出了该模型的测试结构,进行了流片和测量。实测结果表明,该模型能够较好地表征超深亚微米电路的高速互连串扰效应,能够定量计算片上互连线间的耦合串扰,给出不同工艺的互连线长度的优化值。     

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis

Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the K^th-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability.     

高速互连线间的串扰规律研究

信号完整性中的串扰问题是目前高速电路设计中的难点和重点问题.利用高速电路仿真软件HSPICE和MATLAB软件,对高速电路中的互连线串扰模型进行了仿真分析,总结了三种变化因素下互连线问的串扰规律,对部分串扰规律进行了探索性的研究.     

集成电路Cu互连线的XRD研究

对硫酸盐体系中电镀得到的Cu镀层,使用XBD研究不同电沉积条件、不同衬底和不同厚度镀层的织构情况和择优取向.对比了直流电镀和脉冲电镀在有添加剂和无添加剂条件下的织构情况.实验结果表明,对于在各种条件下获得的1 μm Cu镀层,均呈现(111)晶面择优,这样的镀层在集成电路Cu互连线中有较好的抗电迁移性能.