Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Full Field Temperature Measurement of Specular Wafers During Rapid Thermal Processing

Many of the processes involved in the creation of semiconductor devices involve high-temperature processing of silicon wafers. The benefits of reduced thermal budget and faster cycle time make rapid thermal processing (RTP) a possible key technology for semiconductor manufacturing. However, the problem of nonuniform wafer temperature has prevented it from further spread among the industry. The first step in developing controls to maintain a uniform wafer temperature is accurate temperature measurement during processing. In this paper, a system was developed to exploit the specular reflectivity of silicon wafers and obtain a measurement of the wafer temperature profile. The spectral reflectivity is determined by measuring the intensity of an incident beam and the beam reflected from the wafer surface. With this measured reflectivity value the spectral-directional wafer emissivity was determined using Kirchhoff's law. The obtained emissivity then was used to calculate the wafer temperature profile from an image obtained with an infrared camera. An experimental study of the transmittance of an undoped silicon calibration wafer at an elevated temperature is also discussed     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Model-based emissivity correction in pyrometer temperature controlof rapid thermal processing systems

Single-wavelength pyrometers are most often used to infer wafer temperature in rapid-thermal-processing (RTP) systems. A constant wafer emissivity is assumed with a pyrometer, but a variation in the wafer's surface emissivity can result in an error in the inferred temperature which affects the temperature control of the RTP system. A time-dependent variation is evident in rapid thermal chemical vapor deposition where the emissivity is a function of the film type and thickness. An approach which uses a physically based model of the emissivity variation as part of the feedback control loop is described. The technique employs a first-order model of the emissivity as a function of film thickness from which a projected actual wafer temperature is inferred. The film thickness is approximated using a valid growth-rate expression and temperature as a function of time. These models are then incorporated into the feedback loop of the RTP control system     

Using wavelength-dependent emissivity of semiconductor wafer tomodel heat transfer in rapid thermal processing station

This paper develops an approach for using a wavelength-dependent emissivity model of a semiconductor wafer in calculating heat transfer in a rapid thermal processing (RTP) station. The wafer emissivity is modeled by a generalized polynomial in wavelength where the coefficients may be functions of temperature. A comparison of experimental data with simulated results for a silicon wafer is provided     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

Thermal and stress analysis of semiconductor wafers in a rapidthermal processing oven

Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed     

Transient thermal behavior in a new RTP chamber

The transient thermal behavior of 200 and 300 mm wafers in a new rapid thermal processing (RTP) chamber is investigated. The AST3000 is a new RTP tool to meet the process requirements for both wafer sizes in 0.18 μm technologies and beyond. In this paper, experimental results obtained on both 200 and 300 mm wafers for varying processing conditions are shown: spike anneal experiments with fast ramp rates up to 200°C/s were performed. For standard anneal recipes, the steady state time is varied in a broad range and also the inherent temperature uniformity is investigated.     

Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

Semi-Empirical Model-Based Multivariable Iterative Learning Control of an RTP System

Comprehensive study on control system design for a rapid thermal processing (RTP) equipment has been conducted with the purpose to obtain maximum temperature uniformity across the wafer surface, while precisely tracking a given reference trajectory. The study covers from model development, identification, optimum multivariable iterative learning control (ILC), to reduced-order controller design. The highlight of the study is the ILC technique on the basis of a semi-empirical dynamic radiation model named as$T^4$-model. It was shown that the$T^4$-model-based ILC technique can remarkably improve the performance of RTP control compared with the ordinary linear model-based ILC. In addition, reduced-order control methods and the associated optimum sensor location have been addressed. The proposed techniques have been evaluated in an RTP equipment fabricating 8-in wafers.     

The effect of patterned susceptor on the thickness uniformity ofrapid thermal oxides

A temperature compensation concept suitable for rapid thermal processing (RTP) with a nonuniform wafer temperature distribution is proposed in this work. Concentric Si rings with different diameters are placed on planar quartz or Si susceptors and are regarded as patterned susceptors for temperature compensation. We put monitor wafers on the patterned susceptor and see the effect of the patterned susceptor on the oxide thickness uniformity of the monitor wafers. The Si rings work as radiation barriers when placed on the quartz susceptor, but as heat conduction media when placed on the Si susceptor. By properly arranging the Si rings on the planar susceptors, the monitor wafers' oxide thickness uniformity can be improved     

Control of MMST RTP: repeatability, uniformity, and integration forflexible manufacturing [ICs]

A real-time multivariable strategy is used to control the uniformity and repeatability of wafer temperature in rapid thermal processing (RTP) semiconductor device manufacturing equipment. This strategy is based on a physical model of the process where the model parameters are estimated using an experimental design procedure. The internal model control (IMC) law design methodology is used to automatically compute the lamp powers to a multizone array of concentric heating zones to achieve wafer temperature uniformity. Control actions are made in response to real-time feedback information provided by temperature sensing, via pyrometry, at multiple points across the wafer. Several modules, including model-scheduling and antiovershoot, are coordinated with IMC to achieve temperature control specifications. The control strategy, originally developed for prototype equipment at Stanford University, is analyzed via the customization, integration, and performance on eight RTP reactors at Texas Instruments conducting thirteen different thermal fabrication operations of two sub-half-micron CMOS process technologies used in the the Microelectronics Manufacturing Science and Technology (MMST) program     

A methodology for analysis of RTCVD systems

A methodology for predicting the spatial and temporal distribution of film thickness is given for low pressure chemical vapor deposition (LPCVD) in rapid thermal processor (RTP) systems. The methodology is based on a model for the heat transfer to, from, and within the wafer, a geometric ray trace algorithm to predict the radiant heat transfer from the lamps and reflectors to the wafer, a deposition model for the deposited film thickness, and an optical properties model that gives the wafer absorptivity and emissivity. The modeling is for low pressure processes, where gas flow effects are secondary, and concentrates on the radiant heat transfer to and from the wafer. The methodology is based on physical principles, with a minimum reliance on empirical and experimental data, and has been validated by comparison with deposited films from a cylindrical RTP system     

快速热处理对PECVD氮化硅薄膜性能的影响

利用PECVD在硅片上沉积了氮化硅(SiNx)薄膜,将沉积膜后的样品放在N2气氛中进行快速热处理(RTP),研究了不同快速热处理对PECVD氮化硅薄膜件能的影响.采用原子力显微镜(AFM)检测薄膜的表面形貌,利用椭圆偏振仪测量样品膜厚和折射率,利用准稳态光电导衰减法(QSSPCD)测鼋样品的少子寿命.实验结果表明随着RTP温度的升高,薄膜厚度迅速减小,折射率迅速增大;低于500℃热处理时,少子寿命基本不变;高于500℃热处理时,随着温度的升高,少子寿命急剧下降.氮化硅薄膜经热处理后反射率基本不变.     

快速热处理设备的电流环数字放大器设计

硅晶圆快速热处理（Rapid Thermal Processing,RTP）过程中,对于加热温度及温度均匀性的精确控制是保证晶圆热处理质量的关键。针对自行研制的RTP设备,通过分析其加热特性,初步建立了数学模型,设计了基于FPGA的电流环数字放大器。利用Matlab对电流控制器进行了优化与仿真,证明在保证稳态精度的情况下,电流环数字放大器能够提供系统准确稳定的电流输入,同时兼有电压闭环控制,从而可以实时监控输入负载的能量,这样就可以很好地解决快速升温中过冲问题。     

Manufacturing issues related to RTP induced overlay errors in aglobal alignment stepper technology

The effect of rapid thermal processing on wafer distortion and overlay accuracy in global alignment photolithography in the fabrication of 0.85 μm CMOS Flash EPROM integrated circuits was studied. Both rapid thermal process parameters and system design (single and multi-lamp processors) were evaluated for their effect on overlay accuracy. It was found that a rapid thermal process (following contact etch and ion implantation) at set temperatures greater than or equal to 950°C resulted in interconnect metallization-to-contact overlay errors in excess of 1.0 μm across the wafer, which led to a 20% functional circuit yield loss. In the case of the single lamp processor, this misalignment was attributed to wafer distortion due to the temperature overshoot during the ramp step, which subsequently resulted in an across wafer temperature range of greater than 120°C. This temperature overshoot and nonuniformity was eliminated by reducing the ramp rate below 100°C/s. This ramp rate reduction, however, decreased the system wafer throughput, and required optimization to eliminate the overlay errors and minimize the effect on throughput. In this study, a 60°C/s ramp rate was found to be optimum. For the multi-lamp RTP system, the metal-to-contact overlay error was not observed. This was believed to be due to the design of the heating mechanism in the multi-lamp processor, which did not produce the large wafer temperature overshoot and nonuniformity that was observed in the single lamp processor     

Thermal uniformity of 12-in silicon wafer during rapid thermalprocessing by inverse heat transfer method

Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated