Impact of electron and hole inversion-layer capacitance on lowvoltage operation of scaled n- and p-MOSFET's

The influence of inversion-layer capacitance (C_inv) on supply voltage (V_dd) of n- and p-MOSFET's is quantitatively examined. The physical origin of the effect of C_inv on V_dd consists in the band bending of a Si substrate in the inversion condition due to C_inv, which is not scaled with a reduction in gate oxide thickness. The amount and the impact of the band bending is accurately evaluated on a basis of one dimensional (1-D) self-consistent calculations including two-dimensional (2-D) subband structure of inversion-layer electrons and holes. It is demonstrated that additional band bending of a Si substrate due to C_inv becomes a dominant factor to limit the lowering of V_dd for CMOS with ultrathin gate oxides. The operation at V_dd lower than 0.6 V is quite difficult even with effective T_ox less than 1 nm     

Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Anticipation of nitrided oxides electrical thickness based on XPS measurement

Plasma nitridation of thermally grown oxide films has proven to be an excellent gate dielectric in meeting the electrical requirements of the 65 nm node. As the 65 nm device performance is very sensitive to both physical thickness and nitrogen dose of these dielectric films, it is highly desirable to predict the electrical properties of such films. We present a simple physical model to forecast the capacitance-equivalent thickness (CET) of nMOS devices for 65 nm technology. The model is based on the total nitrogen dose and the dielectric physical thickness, both given by in-line X-ray photoelectron spectroscopy (XPS) measurement of the plasma nitrided gate dielectric. This model uses an estimated gate oxide dielectric constant, the gate depletion capacitance and the inversion layer capacitance. A good correlation is obtained between calculated and measured CET for plasma nitrided oxides from 19 to 30 Å CET and for a large range of incorporated nitrogen doses.     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

Impact of tunnel currents and channel resistance on thecharacterization of channel inversion layer charge and polysilicon-gatedepletion of sub-20-Å gate oxide MOSFETs

This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-Å oxide MOS devices, transistors with channel lengths less than about 10 μm will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance     

1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O)composites prepared by RPECVD/oxidation process

Ultrathin nitride/oxide (~1.5/0.7 nm) dual layer gate dielectrics have been formed using remote plasma enhanced CVD of nitride onto plasma-grown oxide interface layers. High accumulation capacitance (1.72 μF/cm²) is measured and the equivalent oxide thickness is 1.6 nm after quantum effect corrections. Compared to 1.6 nm oxides, a tunneling current reduction of more than 100 fold is found for devices with 1.6 nm N/O dielectrics due to increased film thickness and interface nitridation. Hole channel mobility decreases by about 5%, yielding very good P-MOSFET current drive. Excellent dielectric reliability and interface robustness are also demonstrated for P-MOSFET's with N/O dielectrics     

Electrical characterization of semiconductor materials and devices using scanning probe microscopy

Several scanning probe microscopy (SPM) modes exist for the electrical characterization of semiconductor materials and devices with nm-scale resolution. The most important electrical SPM modes are: scanning capacitance microscopy (SCM), scanning spreading resistance microscopy (SSRM), and tunneling-AFM (TUNA). SCM and SSRM are primarily used for 2-D carrier profiling and resistivity mapping on cross-sectioned devices. The spatial resolution is on the order of 20 nm, while the dynamic range goes from 10¹⁵ to 10²⁰ atoms/cm³. Imaging examples are shown for sub-quarter micron MOSFETs, ferro-electric material, and compound semiconductor structures. The TUNA method allows one to perform thickness mapping and defect imaging of thin dielectric films using a tunneling current flowing between the SPM tip and the sample. Spatial resolution is on the nm-scale, while the current range is from 50 fA to 120 pA. Examples are shown of gate oxide breakdown and defect localization in thin gate oxides.     

A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.     

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

RTD/2-D MESFET logic element for compact, ultra-low-powerelectronics

We describe compact and highly functional logic elements utilizing a two-dimensional (2-D) MESFET with a resonant tunneling diode load. The 2-D MESFET uses two lateral Schottky gate contacts to modulate the width of the 2-D electron gas layer. The novel contact geometry results in reduced gate capacitance, ultra-low-power performance, and the elimination of the Narrow Channel Effect (NCE) compared to conventional HFETs or MESFETs. The advantage of using an RTD as the load device is the reduction of the static power consumption at the logical high input level. We demonstrate low-power RTD/2-D MESFET inverter operation as well as compact NAND and NOR gates using a single RTD/2-D MESFET pair. We also present optimized inverter elements and estimate from SPICE simulations the power-delay products of RTD/2-D MESFET ring oscillators. Compared to recently reported values for CMOS on SOI, the RTD/2-D MESFET technology is expected to exhibit one order of magnitude less active power dissipation and a factor of 3 lower power-delay product     

Modeling for reduced gate capacitance of nanoscale MOSFETs

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the polysilicon electrodes. For the first time, based on least-squares curve fit, we quantitatively explore the impact of quantum mechanics effects in polysilicon gate region on gate capacitance. Comparing the theoretical curves with an extensive set of simulation ones has validated this model.     

Impact of gate-poly grain structure on the gate-oxide reliability[CMOS]

Time dependent dielectric breakdown of thin oxides, 1.5 to 5.0 nm has been studied for different gate-poly grain structures. The poly grain was varied by the poly deposition, and the source-drain (S/D) rapid thermal anneal (RTA) conditions. The study, which was done on fully fabricated CMOS devices, showed substantial reliability degradation in thin gate oxides (below 2.0 nm), when using S/D RTA temperatures above 1000°C. The results can be explained in terms of the interface roughness at the gate poly interface induced by the S/D RTA temperature above the viscoelastic point of the SiO₂. A possible mechanism for the drastic reliability degradation in thin gate oxides, is the protrusion of poly grains into the softening oxide at high temperature     

Mercury-probe characterisation of soft breakdown: effect of oxide thickness and measurement set-up

The breakdown of 4–7 run gate oxides is investigated using fast-feedback Hg-probe measurements to perform Exponentially Ramped Current Stress (ERCS) tests. Soft breakdown is detected in oxides thinner than 5 nm. However, it is found that the detection of soft-breakdown during ERCS test depends on the measurement set-up. In particular, it can be completely suppressed by reducing the gate oxide capacitor area. The consequences of this result for correct routine assessment of gate oxide integrity in microelectronic manufacturing are discussed.     

The effects of interfacial sub-oxide transition regions andmonolayer level nitridation on tunneling currents in silicondevices

Direct tunneling (D-T) in Si metal-oxide-semiconductor (MOS) devices having 1.8 to 3 nm thick gate oxides is reduced approximately tenfold by monolayer Si-dielectric interface nitridation with respect to devices with nonnitrided interfaces. The reduction is independent of gate oxide-equivalent thickness, and gate or substrate injection, and extends into the Fowler-Nordheim tunneling (F-N-T) regime for thicker oxides as well. A barrier layer model, including sub-oxide transition regions, has been developed for the interface electronic structure for tunneling calculations using X-ray photoelectron spectroscopy data. These calculations provide a quantitative explanation for the observed tunneling current reductions     

A metal-gate self-aligned MOSFET using nitride oxide

A new method for making metal-gate self-aligned transistors using a thin nitrided oxide (12 nm) as a gate dielectric has been demonstrated. The nitrided thermal oxide acts as both a local oxidation mask and the final gate dielectric to produce a self-aligned thick oxide in the source-drain region. The thick oxide reduces the overlap capacitance down to that of a self-aligned polysilicon-gate device while allowing the use of a metal gate with a much lower resistivity than the more commonly used polycrystalline silicon. A high-frequency capacitance-voltage technique has been used to measure gate to source-drain overlap capacitance. The overlap capacitance was measured for a range of source-drain oxide thicknesses from 370 down to 255 nm. The capacitance increased from 0.64 to 0.74 fF/µm. The overlap capacitance of a self-aligned polycrystalline silicon-gate device with similar processing parameters was 0.98 fF/µm. The channel mobility has been determined to be approximately 350 cm²/V . s. Transistors with channel lengths as low as 0.7/µm were fabricated. Ring oscillators were also fabricated with stage-delays as low as 300 ps at 1.5 V and power-delay products of 70 fJ.     

Capacitance reconstruction from measured C-V in high leakage,nitride/oxide MOS

A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) curves in high leakage dielectric MOSFETs is presented. An RC network is used to accommodate the distributed nature of MOSFETs and an optimization technique is applied to extract the intrinsic gate capacitance. Applicability of the method is demonstrated for ultra-thin nitride/oxide (N/O ~1.4 nm/0.7 nm) composite dielectric MOSFETs     

Alpha-particle-induced collected charge model in SOI-DRAM's

We have developed a model for collected charges induced by an alpha-particle for SOI-DRAMs which assumes that the body capacitance equals the gate capacitance and that holes do not recombine with electrons. The validity of our model was supported by three-dimensional (3-D) device simulations that considered various gate lengths, gate oxide thicknesses, and flat-band voltages. The work function difference between the gate and body materials caused a significant increase in the current gain. The vertical band of the body region should therefore be flat to suppress the collected charge. A thinner gate oxide would also suppress the collected charge during a refresh interval. This finding could not be obtained from the conventional equation